Dynamic Random Access Memory Unit And Method For Fabricating The Same
    111.
    发明申请
    Dynamic Random Access Memory Unit And Method For Fabricating The Same 有权
    动态随机存取存储单元及其制造方法

    公开(公告)号:US20140054546A1

    公开(公告)日:2014-02-27

    申请号:US13703722

    申请日:2012-10-18

    摘要: A dynamic random access memory unit and a method for fabricating the same are provided. The dynamic random access memory unit comprises: a substrate; an insulating buried layer formed on the substrate; a body region formed on the insulating buried layer and used as a charge storing region; two isolation regions formed on the body region, in which a semiconductor contact region is formed between the isolation regions and is a charge channel; a source, a drain and a channel region formed on the isolation regions and the semiconductor contact region respectively and constituting a transistor operating region which is partially separated from the charge storing region by the isolation regions and connected with the charge storing region via the charge channel; a gate dielectric layer formed on the transistor operating region, a gate formed on the gate dielectric layer; a source metal contact layer, a drain metal contact layer.

    摘要翻译: 提供了动态随机存取存储单元及其制造方法。 动态随机存取存储器单元包括:衬底; 形成在基板上的绝缘掩埋层; 形成在绝缘掩埋层上并用作电荷存储区域的体区; 形成在体区的两个隔离区,其中在隔离区之间形成半导体接触区,并且是电荷通道; 分别形成在所述隔离区域和所述半导体接触区域上的源极,漏极和沟道区域,并且构成晶体管工作区域,所述晶体管工作区域由所述隔离区域部分地与所述电荷存储区域分离,并且经由所述充电沟道与所述电荷存储区域连接 ; 形成在所述晶体管工作区上的栅介质层,形成在所述栅介质层上的栅极; 源极金属接触层,漏极金属接触层。

    MOS transistor structure with in-situ doped source and drain and method for forming the same
    112.
    发明授权
    MOS transistor structure with in-situ doped source and drain and method for forming the same 有权
    具有原位掺杂源极和漏极的MOS晶体管结构及其形成方法

    公开(公告)号:US08642414B2

    公开(公告)日:2014-02-04

    申请号:US13132768

    申请日:2011-01-19

    申请人: Jing Wang Lei Guo Jun Xu

    发明人: Jing Wang Lei Guo Jun Xu

    IPC分类号: H01L21/336

    摘要: A MOS transistor structure with an in-situ doped source and/or drain and a method for forming the same are provided. The method comprises steps of: providing a substrate; forming a high Ge content layer on the substrate; forming a gate stack on the high Ge content layer and forming a side wall of one or more layers on both sides of the gate stack; etching the high Ge content layer to form a source region and/or a drain region; and forming a source and/or a drain in the source region and/or the drain region respectively by a low-temperature selective epitaxy, and introducing a doping gas during the low-temperature selective epitaxy to heavily dope the source and/or the drain and to in-situ activate a doping element.

    摘要翻译: 提供具有原位掺杂源极和/或漏极的MOS晶体管结构及其形成方法。 该方法包括以下步骤:提供衬底; 在所述基板上形成高Ge含量层; 在高Ge含量层上形成栅极叠层,并在栅叠层的两侧形成一层或多层的侧壁; 蚀刻高Ge含量层以形成源区和/或漏区; 以及通过低温选择性外延分别在源区和/或漏区中形成源极和/或漏极,并且在低温选择性外延期间引入掺杂气体以使源极和/或漏极 并原位激活掺杂元素。

    MOBILE DEVICE WITH SELECTIVE WLAN RECEIVE GAIN LEVELS AND RELATED METHODS
    113.
    发明申请
    MOBILE DEVICE WITH SELECTIVE WLAN RECEIVE GAIN LEVELS AND RELATED METHODS 审中-公开
    具有选择性WLAN的移动设备接收增益水平和相关方法

    公开(公告)号:US20140024410A1

    公开(公告)日:2014-01-23

    申请号:US13552753

    申请日:2012-07-19

    IPC分类号: H04W88/06 H04W52/52

    CPC分类号: H04W52/36 H04W88/06

    摘要: A mobile wireless communications device may include a housing, a cellular transceiver carried by the housing and to operate at a given transmit power level from among different transmit power levels, and a WLAN transceiver carried by the housing and to operate at a given receive gain level from among different receive gain levels. The mobile wireless communications device may also include a controller to select the given receive gain level based upon the given transmit power level of the cellular transceiver.

    摘要翻译: 移动无线通信设备可以包括外壳,由外壳承载的蜂窝收发器,并且在不同发射功率电平之间的给定发射功率电平下操作,以及由外壳承载并在给定的接收增益级别 从不同的接收增益水平。 移动无线通信设备还可以包括控制器,用于基于蜂窝收发器的给定发射功率电平来选择给定的接收增益电平。

    Architecture and control of Reed-Solomon list decoding
    114.
    发明授权
    Architecture and control of Reed-Solomon list decoding 失效
    Reed-Solomon列表解码的架构与控制

    公开(公告)号:US08635513B1

    公开(公告)日:2014-01-21

    申请号:US13363898

    申请日:2012-02-01

    IPC分类号: H03M13/00

    摘要: Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes.

    摘要翻译: 提供了用于在里德 - 所罗门(RS)纠错系统中实现列表解码的系统和方法。 检测器可以从信道提供判决码字,并且还可以为判决码字提供软信息。 软信息可以被组织成用于列表解码的错误事件的组合的顺序。 RS解码器可以使用使用流水线列表解码器架构的列表解码器。 列表解码器可以包括可以并行计算综合征的一个或多个综合征修改电路。 长分割电路可以包括并行地计算多个商多项式系数的多个单元。 列表解码器可以采用迭代解码和有效性测试来产生错误指示符。 迭代解码和有效性测试可以使用较低的综合征。

    Basic matrix based on irregular LDPC, codec and generation method thereof
    115.
    发明授权
    Basic matrix based on irregular LDPC, codec and generation method thereof 有权
    基于不规则LDPC的基本矩阵,编解码器及其生成方法

    公开(公告)号:US08607125B2

    公开(公告)日:2013-12-10

    申请号:US11795826

    申请日:2005-05-13

    IPC分类号: H03M13/00

    摘要: The codec includes an encoding/decoding operation module and a basic matrix storage module. In the stored basic matrix Hb, for all girths with length of 4, any column element of i, j, k or l constituting the girths in anti-clockwise or clockwise always satisfies inequality: (i−j+k−1) mod z≠0, wherein z is the extension factor. When generating the basic matrix, firstly the number of rows M, number of columns N, and weight vectors of the rows and columns are determined, an irregularly original basic matrix is constructed; then the position of ‘1’ is filled by a value chosen from set {0, 1, 2, . . . , z−1} to obtain the basic matrix Hb. The basic matrix Hb obtained by storing constitutes the desired encoder/decoder. The encoder/decoder according to the present invention can effectively eliminate error-floor phenomenon of LDPC codes and accelerate the falling speed of BER curve.

    摘要翻译: 编解码器包括编码/解码操作模块和基本矩阵存储模块。 在存储的基本矩阵Hb中,对于长度为4的所有周长,构成反时针或顺时针的周长的i,j,k或l的任何列元素总是满足不等式:(i-j + k-1)mod z <> 0,其中z是扩展因子。 当生成基本矩阵时,首先确定行数M,列数N和行和列的加权向量,构建不规则原始基本矩阵; 那么'1'的位置由从{{0,1,2,...}中选择的值填充。 。 。 ,z-1}以获得基本矩阵Hb。 通过存储获得的基本矩阵Hb构成所需的编码器/解码器。 根据本发明的编码器/解码器可以有效地消除LDPC码的错误现象,加快BER曲线的下降速度。

    Semiconductor device and method for forming the same
    116.
    发明授权
    Semiconductor device and method for forming the same 有权
    半导体装置及其形成方法

    公开(公告)号:US08592864B2

    公开(公告)日:2013-11-26

    申请号:US13499661

    申请日:2011-06-27

    申请人: Jing Wang Jun Xu Lei Guo

    发明人: Jing Wang Jun Xu Lei Guo

    IPC分类号: H01L21/02

    摘要: A semiconductor device and a method for forming the same are provided. The semiconductor device comprises: a substrate (1); an insulating layer (2), formed on the substrate (1) and having a trench (21) to expose an upper surface of the substrate (1); a first buffer layer (3), formed on the substrate (1) and in the trench (21); and a compound semiconductor layer (4), formed on the first buffer layer (3), wherein an aspect ratio of the trench (21) is larger than 1 and smaller than 10, wherein the first buffer layer (3) is formed by a low-temperature reduced pressure chemical vapor deposition process at a temperature between 200° C. and 500° C., and wherein the compound semiconductor layer (4) is formed by a low-temperature metal organic chemical vapor deposition process at a temperature between 200° C. and 600° C.

    摘要翻译: 提供半导体器件及其形成方法。 半导体器件包括:衬底(1); 形成在所述基板(1)上并具有用于露出所述基板(1)的上表面的沟槽(21)的绝缘层(2); 形成在所述基板(1)和所述沟槽(21)中的第一缓冲层(3); 和形成在第一缓冲层(3)上的化合物半导体层(4),其中沟槽(21)的纵横比大于1且小于10,其中第一缓冲层(3)由 在200℃至500℃之间的温度下进行低温减压化学气相沉积工艺,其中化合物半导体层(4)通过低温金属有机化学气相沉积工艺在200℃ ℃和600℃

    FLASH MEMORY AND METHOD FOR FABRICATING THE SAME
    120.
    发明申请
    FLASH MEMORY AND METHOD FOR FABRICATING THE SAME 有权
    闪存及其制造方法

    公开(公告)号:US20130207173A1

    公开(公告)日:2013-08-15

    申请号:US13514591

    申请日:2012-05-22

    IPC分类号: H01L29/788 H01L21/20

    摘要: A flash memory and a method for fabricating the same are provided. The flash memory comprises: a semiconductor substrate; a storage medium layer formed on the semiconductor substrate and comprising from bottom to top: a tunneling oxide layer, a silicon nitride layer and a blocking oxide layer; a semiconductor layer formed on the storage medium layer and comprising a channel region and a source region and a drain region located on both sides of the channel region respectively; and a gate stack formed on the channel region and comprising a gate dielectric and a gateformed on the gate dielectric.

    摘要翻译: 提供闪速存储器及其制造方法。 闪存包括:半导体衬底; 在半导体衬底上形成的存储介质层,包括从底部到顶部:隧道氧化物层,氮化硅层和阻挡氧化物层; 形成在所述存储介质层上的半导体层,分别包括位于所述沟道区两侧的沟道区和源极区和漏极区; 以及栅极堆叠,其形成在沟道区上并且包括栅极电介质和栅极形成在栅极电介质上。