公开(公告)号：US06813212B2

公开(公告)日：2004-11-02

申请号：US10450276

申请日：2003-06-11

申请人： Hiroyuki Takahashi ,  Takashi Kusakari

发明人： Hiroyuki Takahashi ,  Takashi Kusakari

IPC分类号： G11C800

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C2211/4067

摘要： Problems are prevented that a refresh provides an influence to a normal access and that a continuation of write operations inhibits refresh. In a semiconductor memory device, a clock signal providing a reference to a time interval of refresh operations based on addresses corresponding to a single row s generated as a refresh clock signal. A transition of an access address “Address” externally supplied and corresponding to a memory cell is detected, so that a refresh operation is executed to a memory cell corresponding to a refresh address by triggering the generation of this detection signal before an access to a memory cell designated by the access address is made, wherein the upon input of a write enable signal /WE, the refresh is executed by triggering this signal before a write operation is executed and the refresh operation by triggering the generation of the access address is discontinued in a predetermined period of time based on the refresh clock signal.

摘要翻译： 防止刷新对正常访问产生影响并且写入操作的继续禁止刷新的问题。 在半导体存储器件中，提供基于对应于作为刷新时钟信号生成的单行s的地址的刷新操作的时间间隔的时钟信号。 检测外部提供并对应于存储器单元的访问地址“地址”的转换，从而通过在访问存储器之前触发该检测信号的产生来对与刷新地址相对应的存储单元执行刷新操作 进行由访问地址指定的单元，其中，通过输入写入使能信号/ WE，在执行写入操作之前触发该信号来执行刷新，并且通过触发生成访问地址的刷新操作被中断 基于刷新时钟信号的预定时间段。

公开(公告)号：US06768370B2

公开(公告)日：2004-07-27

申请号：US10282500

申请日：2002-10-29

申请人： Hiroyuki Takahashi ,  Nobumitsu Yano ,  Shinji Okumoto

发明人： Hiroyuki Takahashi ,  Nobumitsu Yano ,  Shinji Okumoto

IPC分类号： G05F110

CPC分类号： G05F1/465

摘要： A voltage step-down circuit (100) that may provide an internal voltage (VINT) by reducing an external power source (VDD) has been disclosed. A voltage step-down circuit (100) may include a voltage step-down portion (10) and a compensation current source portion (20). Voltage step-down portion (10) may compare a reference voltage (VREF) with an internal voltage (VINT) and control an output current (I0) accordingly. An internal circuit (1) connected to receive internal voltage (VINT) may transition from a standby state to an active state in accordance with an activation signal. Compensation current source portion (20) may provide a compensation current (Ic) when internal circuit (1) is in a standby state. In this way, voltage step-down portion (10) may be biased to provide sufficient output current (I0) so that a response time may be improved and variations in internal voltage (VINT) may be reduced.

摘要翻译： 已经公开了可以通过减少外部电源（VDD）来提供内部电压（VINT）的电压降压电路（100）。 电压降压电路（100）可以包括电压降压部分（10）和补偿电流源部分（20）。 电压降压部分（10）可以将参考电压（VREF）与内部电压（VINT）进行比较，并相应地控制输出电流（I0）。 连接以接收内部电压（VINT）的内部电路（1）可以根据激活信号从待机状态转换到活动状态。 当内部电路（1）处于待机状态时，补偿电流源部分（20）可提供补偿电流（Ic）。 以这种方式，电压降压部分（10）可以被偏置以提供足够的输出电流（I0），使得可以改善响应时间并且可以减小内部电压（VINT）的变化。

公开(公告)号：US06766111B2

公开(公告)日：2004-07-20

申请号：US10083619

申请日：2002-02-27

申请人： Yukio Uenaka ,  Hiroyuki Takahashi ,  Masahiro Kawasaki

发明人： Yukio Uenaka ,  Hiroyuki Takahashi ,  Masahiro Kawasaki

IPC分类号： G03B1322

CPC分类号： G03B7/26 ,  G02B27/646 ,  G03B5/00 ,  G03B17/00 ,  G03B17/02 ,  G03B17/14 ,  G03B2205/0007 ,  G03B2217/005

摘要： A camera system having a camera body and a photographing lens, which can be mounted to and dismounted from the camera body, includes a determining device which determines a type of the photographing lens in accordance with data received from the photographing lens; and a body controller which has a function to send body data and individual function data to the photographing lens, wherein each of the individual function data is required for a corresponding function that the photographing lens possesses. The body controller sends all the body data to the photographing lens regardless of the type of the photographing lens, and sends a portion of the individual function data which is associated with the type of the photographing lens to the photographing lens.

摘要翻译： 一种具有照相机主体和摄​​影镜头的照相机系统，其可以安装到照相机主体上并从照相机主体上拆下，其中包括一个确定装置，该确定装置根据从摄影镜头接收到的数据确定拍摄镜头的类型; 以及具有将身体数据和单独的功能数据发送到拍摄镜头的功能的身体控制器，其中为拍摄镜头具有的相应功能需要各个功能数据。 身体控制器将所有身体数据发送到拍摄镜头，而不管拍摄镜头的类型如何，并将与拍摄镜头的类型相关联的各个功能数据的一部分发送到拍摄镜头。

公开(公告)号：US06741808B2

公开(公告)日：2004-05-25

申请号：US10075248

申请日：2002-02-15

申请人： Yukio Uenaka ,  Hiroyuki Takahashi ,  Masahiro Kawasaki

发明人： Yukio Uenaka ,  Hiroyuki Takahashi ,  Masahiro Kawasaki

IPC分类号： G03B726

CPC分类号： G03B17/00 ,  G02B27/646 ,  G03B5/00 ,  G03B7/26 ,  G03B17/02 ,  G03B2205/0007 ,  G03B2217/005

摘要： A camera system includes a photographing lens having a lens memory and/or a lens controller, and a camera body including a body controller which can communicate with the lens memory and/or the lens controller; a first power and a second power which can be supplied to the photographing lens. The lens memory and the lens controller operate with the first power and the second power, respectively, when the photographing lens is mounted to the camera body. The body controller supplies the first power to the photographing lens to drive the lens memory to read data from the lens memory, and subsequently disables the lens memory and supplies the second power to the lens controller so that the body controller and the lens controller communicate with each other if the body controller determines, from the lens data, that the photographing lens includes the lens controller.

摘要翻译： 照相机系统包括具有透镜存储器和/或透镜控制器的拍摄镜头，以及包括能够与镜头存储器和/或镜头控制器通信的主体控制器的照相机主体; 可以提供给拍摄镜头的第一功率和第二功率。 当拍摄镜头安装到照相机主体上时，镜头存储器和镜头控制器分别与第一电源和第二电源一起操作。 身体控制器向拍摄镜头提供第一功率以驱动镜头存储器从镜头存储器读取数据，随后禁用镜头存储器并将第二电力提供给镜头控制器，使得身体控制器和镜头控制器与 如果身体控制器从镜头数据确定拍摄镜头包括镜头控制器，则彼此相对。

公开(公告)号：US06728158B2

公开(公告)日：2004-04-27

申请号：US10027461

申请日：2001-12-21

申请人： Hiroyuki Takahashi ,  Eiji Haseo

发明人： Hiroyuki Takahashi ,  Eiji Haseo

IPC分类号： G11C700

CPC分类号： G11C29/785 ,  G11C11/401 ,  G11C29/787 ,  G11C29/83 ,  G11C2029/1208

摘要： A semiconductor memory device (100) including a memory cell array (MARY) and redundant memory cells (RROW) has been disclosed. A stored defect address (FA) may be programmed in a defect address storing circuit (PRG) corresponding with a defective address in the memory cell array (MARY). A controllable impedance device (TN0) may be selectively turned off to reduce a current passing through intact fuses (F01-F02 to Fn1-Fn2). The controllable impedance device (TN0) may be turned off in response to a potential applied to a pad electrode (PD), a predetermined combination of control signals (CS, OE, WE, etc.), or a reset signal (SR) generated by a power on reset circuit (PON). In this way, current may be reduced when defect address storing circuit does not have a stored defective address (FA). Also, current may be reduced during the semiconductor device characterization so that characterization results may be improved.

摘要翻译： 已经公开了包括存储单元阵列（MARY）和冗余存储单元（RROW）的半导体存储器件（100）。 存储的缺陷地址（FA）可以被编程在与存储单元阵列（MARY）中的缺陷地址相对应的缺陷地址存储电路（PRG）中。 可选择性地关闭可控阻抗器件（TN0），以减少通过完整熔丝（F01-F02至Fn1-Fn2）的电流。 响应于施加到焊盘电极（PD）的电位，控制信号（CS，OE，WE等）的预定组合或产生的复位信号（SR），可控电阻器件（TN0）可以被关断 通过上电复位电路（PON）。 以这种方式，当缺陷地址存储电路没有存储的缺陷地址（FA）时，电流可能会减少。 此外，在半导体器件表征期间电流可能会降低，从而可以提高表征结果。

公开(公告)号：US06724664B2

公开(公告)日：2004-04-20

申请号：US10223807

申请日：2002-08-20

申请人： Hiroyuki Takahashi

发明人： Hiroyuki Takahashi

IPC分类号： H03B100

CPC分类号： G11C8/08 ,  H03K19/00361

摘要： In a low-amplitude driver circuit of the present invention, a P-channel MOS transistor is provided between the output signal line to be driven and the internal power supply line, and control is performed so that this P-channel MOS transistor turns on when the low-amplitude driver circuit outputs a high level (Vcc-Vtn). As a result, the output signal line substantially does not float at or above Vcc-Vtn.

摘要翻译： 在本发明的低振幅驱动电路中，在被驱动的输出信号线和内部电源线之间设置P沟道MOS晶体管，进行控制，以使该P沟道MOS晶体管导通， 低幅度驱动电路输出高电平（Vcc-Vtn）。 结果，输出信号线基本上不漂浮在Vcc-Vtn以上。

公开(公告)号：US06714479B2

公开(公告)日：2004-03-30

申请号：US10333935

申请日：2003-01-23

申请人： Hiroyuki Takahashi ,  Masatoshi Sonoda

发明人： Hiroyuki Takahashi ,  Masatoshi Sonoda

IPC分类号： G11C700

CPC分类号： G11C11/40615 ,  G11C8/18 ,  G11C11/406 ,  G11C11/408

摘要： The present invention provides a semiconductor memory device and control method capable of effectively suppressing the generation of operating current originating in noise of address signals provided from the outside without impairing the operating speed during reading and writing. This semiconductor memory device is provided with a filter circuit (102) for removing noise contained in address signals provided from the outside, a circuit system containing an ATD circuit (311) for generating a first address transition detection signal (&phgr;ATD1) by detecting a change in an address signal prior to passing through the filter circuit (102), and a circuit system containing an ATD circuit (321) for generating a second address transition detection signal (&phgr;ATD2) by detecting a change in an address signal after passing through the filter circuit (102). Refresh operation is controlled by first address transition detection signal (&phgr;ATD1), while read/write operation is controlled by second address transition detection signal (&phgr;ATD2). As a result, only the refresh operation is performed in the case noise has been generated, and the generation of operating current is effectively suppressed.

摘要翻译： 本发明提供一种半导体存储器件和控制方法，其能够有效地抑制由外部提供的地址信号的噪声产生，而不损害读取和写入期间的操作速度。 该半导体存储装置设置有用于去除从外部提供的地址信号中包含的噪声的滤波电路（102），包含用于通过检测变化来产生第一地址转换检测信号（phiATD1）的ATD电路（311）的电路系统 在通过滤波器电路（102）之前的地址信号中，以及包含ATD电路（321）的电路系统，用于通过检测通过滤波器之后的地址信号的变化来产生第二地址转换检测信号（phiATD2） 电路（102）。 刷新操作由第一地址转换检测信号（phiATD1）控制，而读/写操作由第二地址转换检测信号（phiATD2）控制。 结果，在产生噪声的情况下仅执行刷新操作，并且有效地抑制了工作电流的产生。

公开(公告)号：US06655451B2

公开(公告)日：2003-12-02

申请号：US10166251

申请日：2002-06-11

申请人： Yoshio Tada ,  Chikara Saeki ,  Hiroyuki Takahashi

发明人： Yoshio Tada ,  Chikara Saeki ,  Hiroyuki Takahashi

IPC分类号： F28F142

CPC分类号： B01D1/065 ,  F28F1/42 ,  F28F1/422

摘要： A heat transfer tube for a falling film type evaporator, in which water spreading characteristics, particularly the water spreading characteristics in the tube axis direction, enhancing the heat transfer ability. Three types of projections 2, 3, and 4 are formed on an external surface 1a of a heat transfer tube body 1. A respective plurality of projections 2 to 4 are arranged spirally in parallel to one another, forming projection groups 2a to 4a. The number of each projection group 2 to 4 is one. Pitches P2 to P4 for the projections 2 to 4 are in the range of 0.35 mm≦P4

摘要翻译： 一种用于降膜型蒸发器的传热管，其中水分散特性，特别是管轴方向的水分散特性，提高了传热能力。 在传热管主体1的外表面1a上形成有三种突起2,3和4.各个突起2至4彼此平行地布置，形成突起组2a至4a。 每个投影组2到4的数量是一个。 突起2至4的间距P2至P4在0.35mm <= P4

公开(公告)号：US06522181B1

公开(公告)日：2003-02-18

申请号：US09640180

申请日：2000-08-17

申请人： Hiroyuki Takahashi

发明人： Hiroyuki Takahashi

IPC分类号： H03L700

CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C8/18

摘要： A semiconductor apparatus includes an input unit and a control unit. The input unit inputs a first signal and a generation signal. The generation signal is generated based on the first signal and a second signal. The control unit controls the input unit such that one of the first signal and the generation signal is outputted. The input unit inputs the first signal prior to the generation signal. The control unit controls the input unit such that the generation signal instead of the first signal is outputted after an expiration of a predetermined time.

摘要翻译： 半导体装置包括输入单元和控制单元。 输入单元输入第一信号和产生信号。 基于第一信号和第二信号产生生成信号。 控制单元控制输入单元，使得第一信号和生成信号中的一个被输出。 输入单元在产生信号之前输入第一信号。 控制单元控制输入单元，使得在预定时间期满之后输出代替第一信号的生成信号。

公开(公告)号：US06518810B1

公开(公告)日：2003-02-11

申请号：US09594934

申请日：2000-06-15

申请人： Hiroyuki Takahashi

发明人： Hiroyuki Takahashi

IPC分类号： H03K3289

CPC分类号： H03K3/35625 ,  H03K3/012 ,  H03K3/0372

摘要： A latch circuit for temporarily storing an input signal and successively outputting the input signal is disclosed, that comprises an input transfer circuit for inputting a reference clock signal, a first inverter for inverting an output signal of the input transfer circuit, a second inverter for inverting an output signal of the first inverter, and a hold transfer circuit for inputting an output signal of the second inverter and outputting it to the first inverter, wherein a second clock signal is input to the gate of the hold transfer circuit, the signal level of the second clock signal becoming high with a predetermined delay against a leading edge of the reference clock signal and becoming low corresponding to a trailing edge of the reference clock signal.

摘要翻译： 公开了一种用于临时存储输入信号并连续输出输入信号的锁存电路，其包括用于输入参考时钟信号的输入传输电路，用于反相输入传送电路的输出信号的第一反相器，用于反相的第二反相器 第一反相器的输出信号和用于输入第二反相器的输出信号并将其输出到第一反相器的保持传输电路，其中第二时钟信号被输入到保持传送电路的栅极，信号电平 第二时钟信号对于参考时钟信号的前沿具有预定的延迟而变高，并且对应于参考时钟信号的后沿变为低。