公开(公告)号：US06635553B1

公开(公告)日：2003-10-21

申请号：US09721048

申请日：2000-11-22

申请人： Thomas H. DiStefano ,  John W. Smith

发明人： Thomas H. DiStefano ,  John W. Smith

IPC分类号： H01L2130

CPC分类号： H01L23/4985 ,  H01L21/4839 ,  H01L23/22 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/642 ,  H01L24/72 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01066 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/118 ,  H05K3/361 ,  H05K3/4084 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2203/063 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49158 ,  H01L2924/00 ,  H01L2224/48

摘要： A microelectronic connection component includes a support such as a dielectric sheet having elongated leads extending along a surface. The leads have terminal ends permanently connected to the support and tip ends releasably connected to the support. The support is juxtaposed with a further element such as a semiconductor chip or wafer, and tip ends of the leads are bonded to contacts on the wafer using a bonding tool advanced through holes in the support. After bonding, the support and the further element are moved away from one another so as to deform the leads.

摘要翻译： 微电子连接部件包括诸如具有沿着表面延伸的细长引线的电介质片的支撑件。 引线具有永久地连接到支撑件的端部端部和可释放地连接到支撑件的尖端端部。 支撑件与诸如半导体芯片或晶片的另外的元件并置，并且引线的尖端使用通过支撑件中的孔前进的焊接工具结合到晶片上的触点。 在粘合之后，支撑件和另外的元件彼此远离，以使引线变形。

公开(公告)号：US06627519B2

公开(公告)日：2003-09-30

申请号：US09963440

申请日：2001-09-27

申请人： Yong-Bum Kwon ,  Jong-Hyun Lee

发明人： Yong-Bum Kwon ,  Jong-Hyun Lee

IPC分类号： H01L2130

CPC分类号： H01L21/76254

摘要： This invention is to manufacturing of SOI (Silicon On Insulator) wafer; with respect to manufacturing of SOI wafer, preparation process of silicon wafer with desired thickness (100), deposition of Alumina (Al2O3) as insulator by an ALE (Atomic Layer Epitaxial) method such as ALCVD, ALD, ASCVD, etc . . . (110), bonding of this wafer with another silicon wafer by various bonding methods (120), Cutting of this bonded wafer by various methods of cutting (130), Polishing the surface of the cut wafer (140). For the insulator material, titanium oxide (TiO2) or tantalum oxide (Ta2O5) can be used other than Alumina (Al2O3) and such bonding process can be done by unibonding method and cutting method can be done by Smart Cut process.

摘要翻译： 本发明是制造SOI（绝缘体上硅）晶片; 关于SOI晶片的制造，具有期望厚度（100）的硅晶片的制备工艺，通过ALC（原子层外延）方法诸如ALCVD，ALD，ASCVD等沉积氧化铝（Al 2 O 3）作为绝缘体。 。 。 （110），通过各种粘合方法（120）将该晶片与另一硅晶片接合，通过各种切割方法切割该接合晶片（130），抛光切割晶片（140）的表面。 对于绝缘体材料，可以使用除氧化铝（Al2O3）之外的氧化钛（TiO 2）或氧化钽（Ta 2 O 5），并且这种接合工艺可以通过单粘合方法进行，切割方法可以通过智能切割工艺进行。

公开(公告)号：US06617225B2

公开(公告)日：2003-09-09

申请号：US10225737

申请日：2002-08-22

申请人： James E. Boyle ,  Robert L. Davis ,  Laurence D. Delaney ,  Raanan Y. Zehavi

发明人： James E. Boyle ,  Robert L. Davis ,  Laurence D. Delaney ,  Raanan Y. Zehavi

IPC分类号： H01L2130

CPC分类号： H01L21/67303 ,  H01L21/67306 ,  H01L21/67316

摘要： A method of fabricating parts of silicon, preferably virgin polysilicon formed by chemical vapor deposition of silane, and assembling them into a complex structure, such as a silicon tower or boat for removably supporting a plurality of silicon wafers during thermal processing. The virgin polysilicon is annealed to above 1025° C. before it is machined into a predetermined shape. After machining, the silicon parts are annealed in an oxygen ambient. The machined parts are then assembled and joined together followed by another anneal of the assembled structure. A preferred embodiment of the tower includes four legs secured on their ends to two bases. A plurality of slots are cut in the legs allowing slidable insertion of the wafers and support for them. The bases may be either virgin poly or monocrystalline silicon and be either integral or composed of multiple parts.

公开(公告)号：US06583031B2

公开(公告)日：2003-06-24

申请号：US09915217

申请日：2001-07-25

申请人： Chuang-Chia Lin

发明人： Chuang-Chia Lin

IPC分类号： H01L2130

CPC分类号： G02B6/3518 ,  B81B3/004 ,  B81B2201/045 ,  B81B2203/058 ,  B81C2201/053 ,  G02B6/3514 ,  G02B6/3546 ,  G02B6/3566 ,  G02B6/357 ,  G02B6/3572 ,  G02B6/358

摘要： A microelectromechanical systems (MEMS) element, MEMS optical switch and MEMS fabrication method are described. The MEMS element comprises a crystalline and moveable element is moveably attached to the substrate. The moveable element includes a perpendicular portion oriented substantially perpendicular to a plane of the substrate. The crystal structure of the perpendicular portion and substrate are substantially similar. The moveable element moveable is moveably attached to the substrate for motion substantially constrained to a plane oriented substantially perpendicular to a plane of the substrate. In at least one position, a part of a perpendicular portion of the moveable element projects beyond a surface of the substrate. The moveable element may be retained in place by a latch. The perpendicular portion may be formed substantially perpendicular portion to the substrate. An array of such structures can be implemented to work as an optical switch. The optical switch may comprise a crystalline substrate and one or more moveable elements moveably attached to the substrate. The MEMS elements may be fabricated by providing a substrate; forming one or more trenches in the substrate to define a perpendicular portion of a element; and moveably attaching the moveable element to a first surface of the substrate; removing a portion of the substrate such that at least a part of the perpendicular portion projects beyond a second surface of the substrate. The various embodiments provide for a robust and reliable MEMS elements that may be simply fabricated and densely packed.

摘要翻译： 描述了微机电系统（MEMS）元件，MEMS光开关和MEMS制造方法。 MEMS元件包括可移动地附接到基底的结晶和可移动元件。 可移动元件包括垂直于基本垂直于基底平面的垂直部分。 垂直部分和基底的晶体结构基本相似。 可移动的可移动元件可移动地附接到基板，用于基本上约束到基本上垂直于基板的平面定向的平面的运动。 在至少一个位置中，可移动元件的垂直部分的一部分突出超过衬底的表面。 可移动元件可以通过闩锁保持在适当的位置。 垂直部分可以形成为基本上垂直于基底的部分。 可以实现这种结构的阵列以用作光学开关。 光学开关可以包括结晶衬底和可移动地附接到衬底的一个或多个可移动元件。 可以通过提供衬底来制造MEMS元件; 在所述衬底中形成一个或多个沟槽以限定元件的垂直部分; 以及将所述可移动元件可移动地附接到所述基板的第一表面; 去除所述基底的一部分，使得所述垂直部分的至少一部分突出超过所述基底的第二表面。 各种实施例提供了可以简单地制造和密集包装的鲁棒且可靠的MEMS元件。

公开(公告)号：US06548375B1

公开(公告)日：2003-04-15

申请号：US09527095

申请日：2000-03-16

申请人： Héctor J. De Los Santos ,  Yu-Hua Kao Lin

发明人： Héctor J. De Los Santos ,  Yu-Hua Kao Lin

IPC分类号： H01L2130

CPC分类号： H01L21/76251 ,  H01L21/2007 ,  H01L21/31612

摘要： A method of directly and indirectly bonding a microwave substrate 14 and a silicon substrate 12 is described. The method for directly bonding a silicon substrate includes the steps of cleaning the microwave substrate and cleaning the silicon substrate. Then, the microwave substrate and the silicon substrate are stacked together. The stack is placed in a furnace. The temperature of the furnace is increased to a predetermined temperature at a predetermined rate. The temperature of the furnace is reduced at a second predetermined rate. The method of indirectly bonding includes sputtering a silicon dioxide layer on the microwave substrate and silicon substrate prior to placing them together.

摘要翻译： 描述了直接和间接地结合微波衬底14和硅衬底12的方法。 直接接合硅衬底的方法包括清洁微波衬底和清洁硅衬底的步骤。 然后，将微波衬底和硅衬底堆叠在一起。 将堆叠放置在炉中。 炉子的温度以预定的速率增加到预定的温度。 炉的温度以第二预定速率降低。 间接结合的方法包括在将微波衬底和硅衬底放置在一起之前溅射二氧化硅层。

公开(公告)号：US06534385B2

公开(公告)日：2003-03-18

申请号：US10003999

申请日：2001-11-14

申请人： Young-Ju Park ,  Sung-Min Hwang ,  Eun-Kyu Kim

发明人： Young-Ju Park ,  Sung-Min Hwang ,  Eun-Kyu Kim

IPC分类号： H01L2130

CPC分类号： H01L21/76251 ,  H01L21/02381 ,  H01L21/02392 ,  H01L21/02463 ,  H01L21/02494 ,  H01L21/02546 ,  H01L21/02658 ,  H01L21/2007 ,  H01L21/76248

摘要： The present invention relates to a method of fusion for heteroepitaxial layers and overgrowth thereon. According to the present invention, a high quality heteroepilayer can be formed by patterning a fused semiconductor layer, overgrowing it with a persistent patterned character, and fusing other semiconductors having different lattice constants by means of utilizing the rate difference between the lateral growth rate and the vertical growth rate exhibited, on the above process. Further, according to the present invention, the lattice constant difference of the two semiconductors can be overcome and a high quality quantum structure can be formed. According to the present invention, the junction of two semiconductor materials having different lattice constants, as well as a good overgrowth on heteroepitaxial layers can be carried out. Accordingly to the present invention, the base material from which the new, as yet on realized, conceptive optoelectronic device can be made.

公开(公告)号：US06521511B1

公开(公告)日：2003-02-18

申请号：US09242923

申请日：1999-02-26

申请人： Satoshi Inoue ,  Tatsuya Shimoda ,  Wakao Miyazawa

发明人： Satoshi Inoue ,  Tatsuya Shimoda ,  Wakao Miyazawa

IPC分类号： H01L2130

CPC分类号： H01L27/1266 ,  B23K26/40 ,  B23K26/57 ,  B23K2103/172 ,  G02F1/13454 ,  G02F1/1362 ,  H01L21/2007 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/76289 ,  H01L27/1214 ,  H01L29/78603 ,  H01L2221/68359 ,  H01L2221/68368

摘要： A thin film device fabrication method in which a thin film device formed on a substrate are transferred to a primary destination-of-transfer part and then the thin film device is transferred to a secondary destination-of-transfer part. A first separation layer (120) made of such a material as amorphous silicon is provided on a substrate (100) which allows passage of laser. A thin film device (140) such as TFTs are formed on the substrate (100). Further, a second separation layer (160) such as a hot-melt adhesive layer is formed on the thin film devices (140), and a primary destination-of-transfer part (180) is mounted thereon. The bonding strength of the first separation layer is weakened by irradiation with light, and the substrate (100) is removed. Thus, the thin film device (140) is transferred to the primary destination-of-transfer part. Then, a secondary destination-of-transfer part (200) is attached onto the bottom of an exposed part of the thin film device (140) via an adhesive layer (190). Thereafter, the bonding strength of the second separation layer is weakened by such means as thermal fusion, and the primary destination-of-transfer part is removed. In this manner, the thin film device (140) can be transferred to the secondary destination-of-transfer part (200) while maintaining layering relationship with respect to the substrate (100).

摘要翻译： 一种薄膜器件制造方法，其中形成在衬底上的薄膜器件被转移到第一转移部件，然后将薄膜器件转移到次级转移部件。 由诸如非晶硅的材料制成的第一分离层（120）设置在允许激光通过的基板（100）上。 在基板（100）上形成诸如TFT的薄膜器件（140）。 此外，在薄膜器件（140）上形成诸如热熔粘合剂层的第二分离层（160），并且其上安装有主要转移部件（180）。 通过照射光使第一分离层的结合强度减弱，并除去基板（100）。 因此，薄膜器件（140）被传送到主要转移部件。 然后，经由粘合剂层（190）将次要转移部件（200）附着到薄膜器件（140）的暴露部分的底部。 此后，第二分离层的结合强度通过热熔融的方式被削弱，并且去除了主要转移部分。 以这种方式，薄膜器件（140）可以在保持与衬底（100）的分层关系的同时被转移到次级转移部件（200）。

公开(公告)号：US06514836B2

公开(公告)日：2003-02-04

申请号：US09873047

申请日：2001-06-04

申请人： Rona Elizabeth Belford

发明人： Rona Elizabeth Belford

IPC分类号： H01L2130

CPC分类号： H01L29/7842 ,  H01L21/76254 ,  Y10S438/938 ,  Y10S438/973

摘要： A new method of producing strained crystalline semiconductor microelectronic devices. Microelectronic devices can either be formed within a membrane, prior to straining or processed after straining. The method includes the steps of straining a membrane along at least one axis and straining using wafer-bonding techniques.

公开(公告)号：US06500732B1

公开(公告)日：2002-12-31

申请号：US09626532

申请日：2000-07-27

申请人： Francois J. Henley ,  Michael A. Brayan ,  William G. En

发明人： Francois J. Henley ,  Michael A. Brayan ,  William G. En

IPC分类号： H01L2130

CPC分类号： H01L21/76254 ,  Y10T156/1158

摘要： A method of forming substrates. The method includes providing a donor substrate; and forming a cleave layer comprising a cleave plane on the donor substrate. The cleave plane extends from a periphery of the donor substrate through a center region of the substrate. The method also includes forming a device layer on the cleave layer. The method also includes selectively introducing a plurality of particles along the periphery of the cleave plane to form a higher concentration region at the periphery and a lower concentration region in the center region. Selected energy is provided to the donor substrate to initiate a cleaving action at the higher concentration region at the periphery of the cleave plane to cleave the device layer at the cleave plane.

摘要翻译： 一种形成基底的方法。 该方法包括提供施主衬底; 以及在所述供体基底上形成包含解理面的切割层。 解理面从施主衬底的周边延伸穿过衬底的中心区域。 该方法还包括在切割层上形成器件层。 该方法还包括选择性地沿着解理面的周边引入多个粒子，以在中心区域的周边形成较高的浓度区域，并在中心区域形成较低的浓度区域。 选择的能量提供给施主衬底，以在分裂面周边的较高浓度区域处引发裂解作用，以在分裂面处切割器件层。

公开(公告)号：US06482719B1

公开(公告)日：2002-11-19

申请号：US08526149

申请日：1995-08-02

申请人： Mohammed Anjum ,  Alan L. Stuber ,  Maung H. Kyaw

发明人： Mohammed Anjum ,  Alan L. Stuber ,  Maung H. Kyaw

IPC分类号： H01L2130

CPC分类号： H01L21/76216 ,  H01L21/823481

摘要： An MOS device is provided having a channel-stop implant placed between active regions and beneath field oxides. The channel-stop dopant material is a p-type material of atomic weight greater than boron, and preferably utilizes solely indium ions. The indium ions, once implanted, have a greater tendency to remain in their position than boron ions. Subsequent temperature cycles caused by, for example, field oxide growth do not significantly change the initial implant position. Thus, NMOS devices utilizing indium channel-stop dopant can achieve higher pn junction breakdown voltages and lower parasitic source/drain-to-substrate capacitances. Furthermore, the heavier indium ions can be more accurately placed than lighter boron ions to a region just below the silicon layer which is to be consumed by subsequent field oxide growth. By fixing the peak concentration density of indium at a depth just below the field oxide lower surface, channel-stop implant region is very shallow. Small dispersions in range allow for more precise control of the indium atoms just below the field oxide, further from the inner bulk material of the underlying substrate.

摘要翻译： 提供了MOS器件，其具有放置在有源区域之间和场氧化物之下的通道停止植入物。 通道阻挡掺杂剂材料是原子量大于硼的p型材料，并且优选仅使用铟离子。 一旦注入，铟离子比硼离子具有更大的保留位置的倾向。 由例如场氧化物生长引起的后续温度循环不会显着改变初始植入位置。 因此，利用铟通道停止掺杂剂的NMOS器件可以实现更高的pn结击穿电压和较低的寄生源/漏极到衬底电容。 此外，较重的铟离子可以比较轻的硼离子更准确地放置在正好在随后的场氧化物生长消耗的硅层之下的区域。 通过在刚好低于场氧化物下表面的深度固定铟的峰浓度密度，通道停止注入区非常浅。 范围内的小分散体允许对场氧化物正下方的铟原子进行更精确的控制，远离底层基底的内部体积材料。