公开(公告)号：US11374777B2

公开(公告)日：2022-06-28

申请号：US16694879

申请日：2019-11-25

Applicant: XILINX, INC.

Inventor： Steve L. Pope ,  David J. Riddoch

IPC: H04L12/18 ,  G06F13/38 ,  H04L49/90

Abstract: A data processing system comprising: a processing subsystem supporting a plurality of consumers, each consumer being arranged to process messages received into a corresponding receive queue; a network interface device supporting a virtual interface for each of the receive queues; and a hardware accelerator coupled to the processing subsystem by the network interface device and configured to parse one or more streams of data packets received from a network so as to, for each consumer: identify in the data packets messages having one or more of a set of characteristics associated with the consumer; and frame the identified messages in a new stream of data packets addressed to a network endpoint associated with the virtual interface of the consumer so as to cause said new stream of data packets to be delivered into the receive queue of the consumer.

公开(公告)号：US11373989B1

公开(公告)日：2022-06-28

申请号：US17006745

申请日：2020-08-28

Applicant: XILINX, INC.

Inventor： Jaspreet Singh Gandhi ,  Suresh Ramalingam

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: A chip package assembly and method of fabricating the same are described herein. The chip package assembly generally includes at least one integrated circuit (IC) die that has had the original solder interconnects at least partially replaced to enhance the reliability of a redistribution layer disposed between the IC die and the substrate. In the resulting chip package assembly, at least one IC die includes first and second pillars extending from exposed contact pads through a first mold compound. The second pillars are fabricated from a material that has a composition different than that of the first pillars. A redistribution layer is formed on the first and second pillars. The solder interconnects mechanically couple the redistribution layer to landing pads of a substrate. The solder interconnects also electrically couple circuitry of the substrate to the circuitry of the IC die through the redistribution layer and first and second pillars.

公开(公告)号：US11373929B1

公开(公告)日：2022-06-28

申请号：US16780305

申请日：2020-02-03

Applicant: XILINX, INC.

Inventor： Gamal Refai-Ahmed ,  Chi-Yi Chao ,  Suresh Ramalingam ,  Hoa Lap Do ,  Anthony Torza ,  Brian Philofsky ,  Arun Kumar Varadarajan Rajagopal

IPC: H01L23/473 ,  H01L23/467 ,  H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L23/427

Abstract: A cooling plate assembly and electronic device having the same are provided which utilize active and passive cooling devices for improved thermal management of one or more chip package assemblies included in the electronic device. In one example, a cooling plate assembly is provided that includes a cooling plate having a first surface and an opposing second surface, a first active cooling device coupled to the first surface of the cooling plate, and a first passive cooling device coupled to the second surface of the cooling plate.

公开(公告)号：US20220197329A1

公开(公告)日：2022-06-23

申请号：US17127525

申请日：2020-12-18

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE

IPC: G06F1/10 ,  H01L23/00

Abstract: Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips. The chip stack includes a clock tree. In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge. The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.

公开(公告)号：US11356379B1

公开(公告)日：2022-06-07

申请号：US16148767

申请日：2018-10-01

Applicant: Xilinx, Inc.

Inventor： Junjie Yan

IPC: H04L47/625 ,  H04L47/25 ,  H04L49/901

Abstract: Apparatus and method relating generally to a channelized communication system is disclosed. In such a method, a read signal and a switch control signal are generated by a controller. Received by channelized buffers are data words from multiple channels associated with groups of information and the read signal. The data words are read out from the channelized buffers responsive to the read signal. A switch receives the data words from the channelized buffers responsive to the read signal. A gap is inserted between the groups of information by the switch. One or more control words are selectively inserted in the gap by the switch responsive to the switch control signal. The switch control signal has indexes for selection of the data words and the control words.

公开(公告)号：US11348624B1

公开(公告)日：2022-05-31

申请号：US17210356

申请日：2021-03-23

Applicant: XILINX, INC.

Inventor： Richard Lewis Walke ,  John Edward Mcgrath

IPC: G11C7/10 ,  G11C8/16

Abstract: Embodiments herein describe a multi-port memory system that includes one or more single port memories (e.g., a memory that can perform only one read or one write at any given time, referred to as a 1W or 1R memory). That is, the multi-port memory system can perform multiple read and writes in parallel (e.g., 1R/1W, 1R/3W, 2R/2W, 3R/1W, etc.) even though the memory in the system can only perform one read or one write at any given time. The advantage of doing so is a reduction in area and power.

公开(公告)号：US11328976B1

公开(公告)日：2022-05-10

申请号：US16808023

申请日：2020-03-03

Applicant: XILINX, INC.

Inventor： Gamal Refai-Ahmed ,  Chi-Yi Chao ,  Suresh Ramalingam ,  Hoa Lap Do ,  Anthony Torza ,  Brian D. Philofsky

IPC: H01L23/367 ,  H01L23/467 ,  H01L23/473 ,  H01L23/42

Abstract: Some examples described herein provide for three-dimensional (3D) thermal management apparatuses for thermal energy dissipation of thermal energy generated by an electronic device. In an example, an apparatus includes a thermal management apparatus that includes a primary base, a passive two-phase flow thermal carrier, and fins. The thermal carrier has a carrier base and one or more sidewalls extending from the carrier base. The carrier base and the one or more sidewalls are a single integral piece. The primary base is attached to the thermal carrier. The carrier base has an exterior surface that at least a portion of which defines a die contact region. The thermal carrier has an internal volume aligned with the die contact region. A fluid is disposed in the internal volume. The fins are attached to and extend from the one or more sidewalls of the thermal carrier.

公开(公告)号：US11327836B1

公开(公告)日：2022-05-10

申请号：US17037382

申请日：2020-09-29

Applicant: XILINX, INC.

Inventor： Danny Tsung-Heng Wu ,  David Tran

IPC: G06F11/00 ,  G06F11/10

Abstract: Some examples herein provide for protection of data on a data path in a memory system in an integrated circuit. In an example, an integrated circuit includes a bit checker circuit, an Error Correcting Code (ECC) encoder circuit, an ECC decoder circuit, and a check bit generation circuit. The bit checker circuit is configured to check write data based on write-path check bit(s). The ECC encoder circuit is configured to generate a write encoded ECC value based on the write data. The write encoded ECC value is to be written to the memory with the write data. The ECC decoder circuit is configured to decode a read encoded ECC value and check read data based on the read encoded ECC value. The read encoded ECC value and read data are read from the memory. The check bit generation circuit is configured to generate read-path check bit(s) from the read data.

公开(公告)号：US11321150B2

公开(公告)日：2022-05-03

申请号：US16540760

申请日：2019-08-14

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  David James Riddoch ,  Kieran Mansley ,  Sian Cathryn James

IPC: G06F7/06 ,  G06F9/54 ,  H04L69/28 ,  H04L69/16 ,  H04L49/90

Abstract: A method and data processing system are provided. The data processing system comprises an application associated with a plurality of sockets and a sub-system for making data available to the application via the plurality of sockets. The sub-system is configured to provide in response to a request from the application: an indication of events that have occurred on one or more of the plurality of sockets; and an indication of an order in which the events should be processed.

公开(公告)号：US11314277B1

公开(公告)日：2022-04-26

申请号：US16532293

申请日：2019-08-05

Applicant: XILINX, INC.

Inventor： Riyas Noorudeen Remla ,  Gourav Modi ,  Azarudin Abdulla ,  Chee Chong Chan

IPC: G06F1/00 ,  G06F1/10 ,  G06F13/42 ,  G06F9/54 ,  G06F9/30 ,  G06F30/34

Abstract: Examples described herein provide a method for reducing lane-to-lane serial skew in an integrated circuit. In an example using a processor-based system, a maximum clock skew is determined from clock skews of respective lanes of a transmitter of the IC. Each of the clock skews corresponds to a skew of a clock signal of the respective lane relative to a same reference clock signal. A skew match amount is determined for each lane of the lanes of the transmitter. The skew match amount for a respective lane of the lanes is based on the maximum clock skew and the clock skew of the respective lane. Configuration data is generated to configure the transmitter to shift incoming data for each lane of the lanes based on the skew match amount for the respective lane.