公开(公告)号：US09846757B2

公开(公告)日：2017-12-19

申请号：US14843805

申请日：2015-09-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Chung-Te Lin ,  Li-Chun Tien

IPC: G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5072 ,  H01L27/0207 ,  H01L27/0924

Abstract: A layout of a cell grid comprises a plurality of polycrystalline silicon (POLY) lines in the cell gird, wherein the POLY lines are arranged horizontally and evenly spaced with a pitch X, and a plurality of fin-shaped oxide diffused (OD) regions in the cell gird, wherein the fin-shaped OD regions are arranged vertically and evenly spaced with a pitch Y, wherein the pitch Y of the fin-shaped OD regions defines width of the cell grid. The layout of the cell grid further comprises a plurality of PMOS transistors and NMOS transistors in the cell grid, wherein the PMOS transistors and NMOS transistors have their source nodes and drain nodes formed in the fin-shaped OD regions and their gates connected to the POLY lines, wherein the plurality of PMOS transistors and NMOS transistors are connected together to form one or more CMOS devices in the cell grid.