公开(公告)号：US20200097442A1

公开(公告)日：2020-03-26

申请号：US16241085

申请日：2019-01-07

Applicant: Ceva D.S.P. Ltd.

Inventor： Jeffrey Allan (Alon) Jacob (Yaakov) ,  Roni M. Sadeh

IPC: G06F15/80 ,  G06F9/30

Abstract: A system and method for performing computational processing by a systolic array. The systolic array including an array of processing elements (PEs) arranged in rows and columns; logic to perform a horizontal shift operation, wherein the horizontal shift operation is performed across the entire systolic array; and logic to mark columns of PEs as enabled or disabled, wherein the systolic array is horizontally divided into horizontal groups, and wherein when performing the horizontal shift operation, valid data that crosses from a first column of PEs of a first horizontal group to a second column of PEs of a second horizontal group is invalidated, wherein the first horizontal group is adjacent to the second horizontal group.

公开(公告)号：US10402196B2

公开(公告)日：2019-09-03

申请号：US14708767

申请日：2015-05-11

Applicant: Ceva D.S.P. Ltd.

Inventor： Roni M. Sadeh ,  Noam Dvoretzki

IPC: G06F9/30

Abstract: A logic circuit in a processor including a plurality of input registers, each for storing a vector containing data elements, a coefficient register for storing a vector containing N coefficients, an output register for storing a result vector, and an arithmetic unit configured to: obtain a pattern for selecting N data elements from the plurality of input registers, select a plurality of groups of N data elements from the plurality of input registers in parallel, wherein each group is selected in accordance with the pattern, and wherein each group is shifted with respect to a previous selected group, perform an arithmetic operation between each of the selected groups and the coefficients in parallel, and store results of the arithmetic operations in the output register.

公开(公告)号：US20180210735A1

公开(公告)日：2018-07-26

申请号：US15877408

申请日：2018-01-23

Applicant: Ceva D.S.P. Ltd.

Inventor： Jeffrey Allan (Alon) JACOB (YAAKOV) ,  Michael Boukaya

IPC: G06F9/38

CPC classification number: G06F9/3804 ,  G06F9/3806 ,  G06F9/3808 ,  G06F9/381 ,  G06F9/3861

Abstract: A system and method is provided for executing a conditional branch instruction. The system and method may include a branch predictor to predict one or more instructions that depend on the conditional branch instruction and a branch mis-prediction buffer to store correct instructions that were not predicted by the branch predictor during a branch mis-prediction.

公开(公告)号：US09952869B2

公开(公告)日：2018-04-24

申请号：US12611937

申请日：2009-11-04

Applicant: Jeffrey Allan (Alon) Jacob (Yaakov) ,  Michael Boukaya

Inventor： Jeffrey Allan (Alon) Jacob (Yaakov) ,  Michael Boukaya

IPC: G06F9/38

CPC classification number: G06F9/3804 ,  G06F9/3806 ,  G06F9/381 ,  G06F9/3861

Abstract: A system and method is provided for executing a conditional branch instruction. The system and method may include a branch predictor to predict one or more instructions that depend on the conditional branch instruction and a branch mis-prediction buffer to store correct instructions that were not predicted by the branch predictor during a branch mis-prediction.

公开(公告)号：US09391738B2

公开(公告)日：2016-07-12

申请号：US14168397

申请日：2014-01-30

Applicant: Ceva D.S.P. Ltd.

Inventor： Noam Dvoretzki ,  Zeev Kaplan ,  Jeffrey Allan (Alon) Jacob (Yaakov)

IPC: H04L27/06 ,  H04L1/00 ,  H04B7/04 ,  H04B7/08 ,  H04L25/03

CPC classification number: H04L1/0054 ,  H04B7/0413 ,  H04B7/0837 ,  H04L1/0047 ,  H04L25/03242 ,  H04L25/03891 ,  H04L2025/03426

Abstract: A decoder to search a tree graph to decode a received signal. The tree graph may have a plurality of levels, each level having a plurality of nodes and each node representing a different value of an element of a candidate transmit signal corresponding to the received signal. The decoder may include a first module to execute a branch prediction at each branch node to select one of a plurality of candidate nodes stemming from the branch node that has a smallest distance increment, and a second module, running in parallel to the first module, to evaluate the branch prediction made by the first module at each branch node by computing an accumulated distance of the selected node. If the accumulated distance of the selected node is greater than or equal to a search radius, the first module may override the branch prediction and select an alternative candidate node.

Abstract translation: 解码器，用于搜索树形图以解码所接收的信号。 树图可以具有多个级别，每个级别具有多个节点，并且每个节点表示对应于接收到的信号的候选发射信号的元素的不同值。 解码器可以包括第一模块，用于在每个分支节点处执行分支预测，以选择源自具有最小距离增量的分支节点的多个候选节点中的一个;以及与第一模块并行运行的第二模块， 通过计算所选节点的累积距离来评估由每个分支节点处的第一模块进行的分支预测。 如果所选节点的累积距离大于或等于搜索半径，则第一模块可以覆盖分支预测并选择替代候选节点。

公开(公告)号：US08320454B2

公开(公告)日：2012-11-27

申请号：US12369849

申请日：2009-02-12

Applicant: Adi Panzer

Inventor： Adi Panzer

IPC: H04N7/12

CPC classification number: H04N19/523

Abstract: Embodiments of the invention are directed to a system and method for sub-pixel motion estimation for video encoding. The method includes providing a best match between a source frame and a reference frame by generating a plurality of non linear building surfaces, generating, in real time, an estimated matching criteria surface representing a matching criteria between the source frame and the reference frame based on the building surfaces and a plurality of sample points of an actual matching criteria surface and selecting, in real time, a position on the estimated matching criteria surface.

Abstract translation: 本发明的实施例涉及用于视频编码的子像素运动估计的系统和方法。 该方法包括通过生成多个非线性构建表面来提供源帧和参考帧之间的最佳匹配，实时地基于代表源帧和参考帧之间的匹配准则的估计匹配准则表面，基于 建筑物表面和实际匹配准则表面的多个采样点，并实时选择估计的匹配准则表面上的位置。

公开(公告)号：US20060150171A1

公开(公告)日：2006-07-06

申请号：US11022852

申请日：2004-12-28

Applicant: Yuval Sapir ,  Michael Boukaya ,  Roy Glasner ,  Eran Briman ,  Hagay Gellis

Inventor： Yuval Sapir ,  Michael Boukaya ,  Roy Glasner ,  Eran Briman ,  Hagay Gellis

IPC: G06F9/45

CPC classification number: G06F9/30181 ,  G06F9/30032 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3828 ,  G06F9/3853 ,  G06F9/3891

Abstract: An instruction packet having an extended machine language instruction may include at least a machine language instruction having encoded bits of an operation and a control word including bits of one or more extension fields. The structure and meaning of the extension fields may depend upon the extended machine language instruction. An association between an extension field and a machine language instruction may depend on the relative position of the extension field and the machine language instruction in the instruction packet.

Abstract translation: 具有扩展机器语言指令的指令分组可以至少包括具有编码的操作位的机器语言指令和包括一个或多个扩展字段的位的控制字。 扩展字段的结构和含义可能取决于扩展的机器语言指令。 扩展字段和机器语言指令之间的关联可以取决于扩展字段和机器语言指令在指令包中的相对位置。

公开(公告)号：US20060149936A1

公开(公告)日：2006-07-06

申请号：US11022850

申请日：2004-12-28

Applicant: Michael Boukaya ,  Roy Glasner ,  Eran Briman

Inventor： Michael Boukaya ,  Roy Glasner ,  Eran Briman

IPC: G06F9/44

CPC classification number: G06F9/3885 ,  G06F9/30101 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/3891

Abstract: A processor core architecture includes a cluster having at least a register file and predefined functional units having access to the register file. The architecture also includes an interface to one or more arbitrary functional units external to the processor core. The interface is to provide the arbitrary functional units with access to the register file.

Abstract translation: 处理器核心架构包括具有至少寄存器文件的集群和具有对寄存器文件的访问的预定义​​功能单元。 该架构还包括到处理器核心外部的一个或多个任意功能单元的接口。 该接口是为任意功能单元提供对寄存器文件的访问。

公开(公告)号：US20250044401A1

公开(公告)日：2025-02-06

申请号：US18361973

申请日：2023-07-31

Applicant: Ceva D.S.P. Ltd.

Inventor： Zeev KAPLAN

IPC: G01S7/02

Abstract: A method and system for finding a Kth element in a series of values, including: organizing the series of values in a PDF by counting a number of occurrences of each value of the series of values; organizing the series of values in a CDF that includes adjacent bins of ranges of values, by counting for each bin an accumulated number of occurrences of values of the series of values up to a bin index of that bin; finding in the CDF a bin for which the associated accumulated number of occurrences is a largest accumulated number of occurrences among the accumulated number of occurrences that is smaller than K; and finding the Kth largest element by searching the PDF for the Kth largest element, starting from the found bin index.

公开(公告)号：US20230269124A1

公开(公告)日：2023-08-24

申请号：US17679944

申请日：2022-02-24

Applicant: Ceva D.S.P. Ltd.

Inventor： Tomer YABLONKA ,  Guy KESHET ,  Zeev KAPLAN

IPC: H04L27/34 ,  H04L25/06 ,  H04L1/00

CPC classification number: H04L27/3405 ,  H04L25/061 ,  H04L1/0054

Abstract: A method and system for performing quadrature amplitude modulation (QAM) decoding of a received signal includes finding for each layer a region in a first constellation diagram of the received signal, the region including a portion of the first constellation diagram, the portion having the same size of a second constellation diagram, and a first constellation order of the received signal is higher than a second constellation order of the second constellation diagram; and, for each layer: finding a first portion of bits based on bits that are constant among constellation points located in the region of the layer; decoding the received signal using a QAM decoder having the second constellation order to obtain a second portion of bits; adjusting the second portion of bits based on the region of the layer; and merging the first portion of bits with the second portion of bits to obtain a decoded symbol.