公开(公告)号：US08143962B1

公开(公告)日：2012-03-27

申请号：US12562165

申请日：2009-09-18

Applicant: Ali Atesoglu

Inventor： Ali Atesoglu

IPC: H03B5/12

CPC classification number: H03B5/1228 ,  H03B5/1212 ,  H03B5/1243 ,  H03J2200/10

Abstract: Tuning circuits with a wide tuning range and a method of tuning an integrated circuit (IC) are disclosed. An embodiment of the disclosed circuits includes varactor banks coupled in series. Each of the varactor banks may include multiple variable capacitors coupled in parallel. A control voltage is routed through the series of varactor banks to adjust the frequency range of the tuning circuit. The control voltage can be selectively routed through one or more of the series of varactor banks based on the operating frequency of the tuning circuit. Enable circuits may be used to control how the control voltage is routed to achieve a specific frequency.

Abstract translation: 公开了具有宽调谐范围的调谐电路和调谐集成电路（IC）的方法。 所公开的电路的实施例包括串联耦合的变容二极管组。 变容二极管组中的每一个可以包括并联耦合的多个可变电容器。 控制电压通过一系列变容二极管组来调节调谐电路的频率范围。 基于调谐电路的工作频率，控制电压可以选择性地路由一系列变容二极管组中的一个或多个。 启用电路可用于控制控制电压如何路由以实现特定频率。

公开(公告)号：US07626440B1

公开(公告)日：2009-12-01

申请号：US11825164

申请日：2007-07-04

Applicant: Ali Atesoglu

Inventor： Ali Atesoglu

IPC: H03L5/00

CPC classification number: H03K19/018528

Abstract: Level shifting circuits and methods are disclosed. One embodiment provides a high speed level shifting circuit that uses an input signal to generate two intermediate signals and uses the intermediate signals to generate an output signal such that voltage stress on individual devices within the level shifting circuit is minimized. One embodiment includes a first driver and second driver coupled in parallel to provide intermediate signals to an output driver. In a particular aspect, individual transistors of the output driver are subject to voltage stresses that are less than the peak-to-peak amplitude of the output signal. In one embodiment, the first driver includes an n-channel metal oxide semiconductor (“NMOS”) cascode circuit, the second driver includes a p-channel metal oxide semiconductor (“PMOS”) cascode circuit, and the output driver includes a complementary metal oxide conductor (“CMOS”) inverter stage. In one embodiment, the level shifter is implemented in an integrated circuit characterized by 45-nanometer technology. In another embodiment, the level shifter is implemented in an integrated circuit characterized by 65-nanometer technology.

Abstract translation: 公开了电平转换电路和方法。 一个实施例提供了一种高速电平移位电路，其使用输入信号来产生两个中间信号，并且使用中间信号来产生输出信号，使得电平移位电路内各个器件上的电压应力最小化。 一个实施例包括并联耦合的第一驱动器和第二驱动器，以向输出驱动器提供中间信号。 在特定方面，输出驱动器的各个晶体管经受小于输出信号的峰 - 峰幅度的电压应力。 在一个实施例中，第一驱动器包括n沟道金属氧化物半导体（“NMOS”）共源共栅电路，第二驱动器包括p沟道金属氧化物半导体（“PMOS”）共源共栅电路，并且输出驱动器包括互补金属 氧化物导体（“CMOS”）逆变器级。 在一个实施例中，电平移位器在以45纳米技术为特征的集成电路中实现。 在另一个实施例中，电平移位器以65纳米技术为特征的集成电路实现。