公开(公告)号：US07761827B1

公开(公告)日：2010-07-20

申请号：US11832425

申请日：2007-08-01

Applicant: Venky Ramachandran ,  Nikhil Tripathi ,  Anmol Mathur ,  Sumit Roy ,  Malay Haldar

Inventor： Venky Ramachandran ,  Nikhil Tripathi ,  Anmol Mathur ,  Sumit Roy ,  Malay Haldar

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/505 ,  G06F2217/78

Abstract: An integrated circuit design system, method, and computer program product are provided that takes into account observability based clock gating conditions. In use, at least one condition is identified where an output of a first logic element is not a function of a first input of the first logic element, due to a second input of the first logic element. To this end, at least one second logic element may be disabled based on the identified condition for power savings or other purposes.

Abstract translation: 提供集成电路设计系统，方法和计算机程序产品，其考虑了基于可观察性的时钟门控条件。 在使用中，由于第一逻辑元件的第二输入，识别出至少一个条件，其中第一逻辑元件的输出不是第一逻辑元件的第一输入的函数。 为此，基于识别的功率节省或其他目的的条件，可以禁用至少一个第二逻辑元件。

公开(公告)号：US07284218B1

公开(公告)日：2007-10-16

申请号：US11084778

申请日：2005-03-18

Applicant: Sumit Roy ,  Gagan Hasteer ,  Anmol Mathur

Inventor： Sumit Roy ,  Gagan Hasteer ,  Anmol Mathur

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: A method and a system for inplace symbolic simulation of circuits. This method is applicable to both single clock and multiple clock domain designs. The method performs inplace symbolic simulation by appending slots to the various objects of the circuit. The slot associated with an object is a function of time, and it represents the functionality of the element at a given time. The method comprises the steps of determining a phase-list, determining ticks associated with each object of the circuit. Based on these ticks, slots are generated. Further, relations between the slots of the various objects of the circuit are captured.

Abstract translation: 一种用于电路的现场符号仿真的方法和系统。 该方法适用于单时钟和多时钟域设计。 该方法通过将插槽附加到电路的各种对象来进行内部符号仿真。 与对象关联的时隙是时间的函数，它表示给定时间的元素的功能。 该方法包括以下步骤：确定相位列表，确定与电路的每个对象相关联的刻度。 基于这些刻度，生成插槽。 此外，捕获电路的各个对象的时隙之间的关系。

公开(公告)号：US06807651B2

公开(公告)日：2004-10-19

申请号：US10172941

申请日：2002-06-17

Applicant: Sanjeev Saluja ,  Anmol Mathur

Inventor： Sanjeev Saluja ,  Anmol Mathur

IPC: G06F1750

CPC classification number: G06F8/443 ,  G06F9/44 ,  G06F17/5045

Abstract: Required precision and information content of datapath signals are used to define functionally safe transformations on data flow graphs. These transformations reduce widths of datapath operators and edges and enhance the mergeability of operators. An algorithm for optimally balancing data flow graph topology to further reduce the data path widths and further enhance mergeability is combined with the above in an iterative algorithm for optimizing DFGs.

Abstract translation: 数据路径信号所需的精度和信息内容用于定义数据流图上的功能安全转换。 这些转换减少了数据路径运算符和边的宽度，并增强了运算符的可合并性。 用于优化平衡数据流图拓扑以进一步减少数据路径宽度并进一步增强可合并性的算法与上述结合使用用于优化DFG的迭代算法。