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    Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance
    11.
    发明授权
    Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance 有权
    具有良好的界面性能的超薄高K栅极电介质，可提高半导体器件的性能

    公开(公告)号：US06911707B2

    公开(公告)日：2005-06-28

    申请号：US09207972

    申请日：1998-12-09

    申请人： Mark I. Gardner ,  Dim-Lee Kwong ,  H. Jim Fulford, Jr.

    发明人： Mark I. Gardner ,  Dim-Lee Kwong ,  H. Jim Fulford, Jr.

    IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L29/51 ,  H01L29/76

    CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： An ultrathin gate dielectric having a graded dielectric constant and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A thin nitrogen-containing oxide, preferably having a thickness of less than about 10 angstroms, is formed on a semiconductor substrate. A silicon nitride layer having a thickness of less than about 30 angstroms may be formed over the nitrogen-containing oxide. The oxide and nitride layers are annealed in ammonia and nitrous oxide ambients, and the nitride layer thickness is reduced using a flowing-gas etch process. The resulting two-layer gate dielectric is believed to provide increased capacitance as compared to a silicon dioxide dielectric while maintaining favorable interface properties with the underlying substrate. In an alternative embodiment, a different high dielectric constant material is substituted for the silicon nitride. Alternatively, both nitride and a different high dielectric constant material may be used so that a three-layer dielectric is formed.

    摘要翻译： 提供具有渐变介电常数的超薄栅极电介质及其形成方法。 认为栅极电介质允许包括晶体管和双栅极存储器单元的半导体器件的增强的性能。 在半导体衬底上形成薄的含氮氧化物，优选具有小于约10埃的厚度。 可以在含氮氧化物上形成厚度小于约30埃的氮化硅层。 氧化物和氮化物层在氨和一氧化二氮环境中退火，并且使用流动气体蚀刻工艺来减少氮化物层的厚度。 与二氧化硅电介质相比，所得到的双层栅极电介质被认为提供增加的电容，同时保持与底层衬底的有利的界面性质。 在替代实施例中，用不同的高介电常数材料代替氮化硅。 或者，可以使用氮化物和不同的高介电常数材料，从而形成三层电介质。

    Wafer arrangement and a method for manufacturing the wafer arrangement
    13.
    发明授权
    Wafer arrangement and a method for manufacturing the wafer arrangement 有权
    晶片布置和晶片布置的制造方法

    公开(公告)号：US08319302B2

    公开(公告)日：2012-11-27

    申请号：US12665876

    申请日：2007-08-08

    申请人： Qingxin Zhang ,  Guo-Qiang Patrick Lo ,  Mingbin Yu ,  Dim-Lee Kwong

    发明人： Qingxin Zhang ,  Guo-Qiang Patrick Lo ,  Mingbin Yu ,  Dim-Lee Kwong

    IPC分类号： H01L31/02

    CPC分类号： B81C3/002 ,  B81C2203/051

    摘要： The wafer arrangement (100) provided comprises a first wafer (101), which comprises an integrated circuit and a recess (105). The wafer arrangement further comprises a portion of a second wafer (103), which comprises a carrier portion and a protrusion (107), the protrusion comprising an active component or actively controlled component (109) such as a MEMS component, wherein the portion of the second wafer (103) is coupled to the first wafer (101) such that the protrusion (107) is received in the recess (105). The invention provides a mechanism for accurately aligning an active component (109) on the second wafer (103) with components on the first wafer (101), such as photonic, electronic or optical components.

    摘要翻译： 提供的晶片布置（100）包括第一晶片（101），其包括集成电路和凹部（105）。 晶片装置还包括第二晶片（103）的一部分，其包括载体部分和突起（107），所述突起包括有源部件或诸如MEMS部件的主动控制部件（109），其中，部分 第二晶片（103）被耦合到第一晶片（101），使得突起（107）被容纳在凹部（105）中。 本发明提供了一种用于将第二晶片（103）上的有源元件（109）与第一晶片（101）上的元件（例如光子，电子或光学元件）精确对准的机构。

    Ultra thin oxynitride and nitride/oxide stacked gate dielectrics fabricated by high pressure technology
    16.
    发明授权
    Ultra thin oxynitride and nitride/oxide stacked gate dielectrics fabricated by high pressure technology 失效
    通过高压技术制造的超薄氧氮化物和氮化物/氧化物层叠栅电介质

    公开(公告)号：US06228779B1

    公开(公告)日：2001-05-08

    申请号：US09187247

    申请日：1998-11-06

    申请人： John A. Bloom ,  Dim-Lee Kwong ,  Robert K. Evans ,  Bruce T. Acker

    发明人： John A. Bloom ,  Dim-Lee Kwong ,  Robert K. Evans ,  Bruce T. Acker

    IPC分类号： H01L2131

    CPC分类号： H01L21/28202 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/518

    摘要： A dense and stable dielectric layer of silicon nitride and silicon dioxide suitable for use in transistors of ULSI circuits is fabricated by a high pressure process in which a nitride layer is first formed on a surface of a silicon substrate and then a silicon dioxide layer is formed on the silicon surface under the nitride layer. By placing the nitride layer above the silicon dioxide and next to a doped polysilicon gate, diffusion of dopant ions such as boron from the gate into the silicon dioxide is reduced. As semiconductor devices are scaled down, the thermal budget required for the process steps is reduced.

    摘要翻译： 适用于ULSI电路的晶体管的氮化硅和二氧化硅的致密且稳定的电介质层通过高压法制造，其中首先在硅衬底的表面上形成氮化物层，然后形成二氧化硅层 在氮化物层下的硅表面上。 通过将氮化物层放置在二氧化硅上方并且靠近掺杂的多晶硅栅极，减少了掺杂剂离子如硼从栅极扩散到二氧化硅中。 随着半导体器件的缩小，减少了工艺步骤所需的热量预算。