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公开(公告)号:US09639490B2
公开(公告)日:2017-05-02
申请号:US13994792
申请日:2011-11-29
申请人: Robert G. Blankenship , Geeyarpuram N. Santhanakrishnan , Yen-Cheng Liu , Bahaa Fahim , Ganapati N. Srinivasa
发明人: Robert G. Blankenship , Geeyarpuram N. Santhanakrishnan , Yen-Cheng Liu , Bahaa Fahim , Ganapati N. Srinivasa
CPC分类号: G06F13/4022 , G06F13/1668 , G06F13/4247 , G06F13/4291 , G06F17/13 , G06F17/5036
摘要: Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.
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公开(公告)号:US20150269104A1
公开(公告)日:2015-09-24
申请号:US13994792
申请日:2011-11-29
申请人: Robert G. Blankenship , Geeyarpuram N. Santhanakrishnan , Yen-Cheng Liu , Bahaa Fahim , Ganapati N. Srinivasa
发明人: Robert G. Blankenship , Geeyarpuram N. Santhanakrishnan , Yen-Cheng Liu , Bahaa Fahim , Ganapati N. Srinivasa
CPC分类号: G06F13/4022 , G06F13/1668 , G06F13/4247 , G06F13/4291 , G06F17/13 , G06F17/5036
摘要: Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.
摘要翻译: 用于在CPU和相关协议之间实现低延迟互连交换机的方法,系统和设备。 CPU被配置为安装在主板上,包括通过CPU插座到插座互连链路链接在一起的多个CPU插槽,形成CPU插座到插座环互连。 CPU也配置为通过CPU插座到插座互连发送数据来相互传输数据。 可以使用诸如QPI的分组协议来传送数据,并且CPU还可以被配置为支持跨CPU的相干存储器事务。
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公开(公告)号:US20130151782A1
公开(公告)日:2013-06-13
申请号:US13324053
申请日:2011-12-13
申请人: Yen-Cheng Liu , Robert G. Blankenship , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Kenneth C. Creta , Sridhar Muthrasanallur , Bahaa Fahim
发明人: Yen-Cheng Liu , Robert G. Blankenship , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Kenneth C. Creta , Sridhar Muthrasanallur , Bahaa Fahim
IPC分类号: G06F12/08
CPC分类号: G06F12/084 , G06F12/0815 , G06F12/0831 , G06F2212/452 , G06F2212/621 , Y02D10/13
摘要: In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.
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