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11.发明授权Process for transporting a cell through a switching structure base on a single stage switch 失效通过单级开关上的开关结构基地传送电池的过程公开(公告)号：US06480501B1
公开(公告)日：2002-11-12
申请号：US09100903
申请日：1998-06-19
申请人： Alain Blanc , Jean-Claude Abbiate
发明人： Alain Blanc , Jean-Claude Abbiate
IPC分类号： H04L1254
CPC分类号： H04L12/5601 , H04L49/153 , H04L49/203 , H04L49/256 , H04L49/309 , H04L49/455
摘要： A process for transporting a data cell throughout a switch fabric having a centralized switching structure and a set of distributed, generally remotely located, Switch Core Access Layers (SCAL) permitting the attachment of the protocol adapters. Remotely with respect to the centralized switching structure, the data cell which is received from a telecommunications link is divided into k logical units (LUs) and additional bytes are introduced for permitting the reservation of a bitmap field that will be used for routing through the switch core. Every LU is coded in accordance with the 8B/10B coding process. Within the centralized switching structure, the k coded LUs are deserialized and the cell clock is obtained for each cell in order to reconstitute the data cell. In addition the routing byte reservations are filled with appropriate values (bit map) for the routing process within the switch by means of an access to an entry routing table. When the cell outputs the switching structure, a second access to a routing table permits the replacement of the previous bit map by new values in order to enhance multicast capabilities. The data cell is divided again in a set of k serialized logical units (LUs) in order to prepare a serialization through k links. The LUs are coded as previously to permit the merging of the LUs when different sets of switches operated in parallel are connected in a port expansion mode. Remotely with respect to the switch core, the coded LUs are deserialized and the data cell is reconstituted by means of the deserialization and extraction of the data cell clock transported by the 8B/10B coding process. The newly inserted values of the bit map are then used for enhancing multicasting capabilities.
摘要翻译： 一种用于在具有集中式交换结构的交换结构中传送数据单元的过程，以及允许协议适配器附接的分布式，通常位于远程位置的交换核心接入层（SCAL）。 远离集中式交换结构，从电信链路接收的数据信元被划分为k个逻辑单元（LU），并且引入附加字节以允许保留将用于通过交换机进行路由的位图字段 核心。 每个LU都按照8B / 10B编码过程进行编码。 在集中式交换结构中，k个编码的LU被反序列化，并且为每个小区获得单元时钟以便重构数据单元。 此外，通过对入口路由表的访问，路由字节预留用交换机内的路由进程的适当值（位图）填充。 当小区输出交换结构时，对路由表的第二次访问允许以先前的位图替换新的值，以便增强多播能力。 为了通过k个链路准备序列化，数据信元再次被划分成一组k个串行化的逻辑单元（LU）。 在以端口扩展模式连接不同组合的并行开关的情况下，逻辑单元按照以前的编码方式允许逻辑单元的合并。 相对于交换机核心，编码的LU被反序列化，并且数据信元通过由8B / 10B编码过程传输的数据信元时钟的反序列化和提取来重构。 然后，使用位图的新插入值来增强多播能力。
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12.发明授权Method and apparatus for automatic functional speed setting of a data circuit terminating equipment 失效数据电路终端设备的自动功能速度设定方法与装置
公开(公告)号：US5247546A
公开(公告)日：1993-09-21
申请号：US719431
申请日：1991-06-24
申请人： Jean-Claude Abbiate , Lucien Quenel
发明人： Jean-Claude Abbiate , Lucien Quenel
CPC分类号： H04L25/0262
摘要： A system implemented in a Data Circuit Terminating Equipment (DCE), interfacing between a user's data processing equipment and a digital network, comprises a detector for generating an Analog Carrier Detect (ACD) DCE internal signal as well as an Analog Squared Data (ASD) DCE internal signal, and an ASD WIDTH ERROR DCE internal signal from the flow of data transmitted by the network and received on the DCE receive line. The system also comprises new circuitry for generating a Lack of Receiver Timing (LRT) DCE internal signal, a Block Error ASD DCE internal signal, and a Block Error Bipolar (BEBIP) DCE internal signal. Finally, the system includes a logical decision process which leads the DCE to automatically adjust its functional speed to the rate of data transmitted by the network and received on DCE receive line. The process includes setting the DCE to the highest possible functional speed, and for that particular speed, checking all four of the ACD, LRT, BEASD and BEBIP DCE internal signals; and if one of the checkings is not satisfactory, setting the DCE to the next possible lower speed, or if all checkings are satisfactory, stopping the process as the DCE is ready to work.
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13.发明授权
公开(公告)号：US5210774A
公开(公告)日：1993-05-11
申请号：US774496
申请日：1991-10-10
CPC分类号： H03H21/0012 , H04L25/0305
摘要： An adaptive equalization system for allowing the equalization of a base-band line of a DCE within a predetermined range, includes an adaptive equalizer for continuously adapting its coefficients in accordance with a predetermined adaptive algorithm. The equalizer includes storage for a plurality of sets of initial coefficients for the equalization process corresponding to a plurality of telecommunication line characteristics and circuits for estimating the energy of the received signal. From the estimation of the energy of the signal on the line, there is derived one set among the plurality of sets of initial coefficients which are then used for setting the equalization before initiating the convergence process. An efficient and very simple equalization process is therefore provided which is ensured to converge whatever the characteristics of the line within the considered range.
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14.发明授权
公开(公告)号：US5196853A
公开(公告)日：1993-03-23
申请号：US797609
申请日：1991-11-25
摘要： Sigma-delta converter for converting an analog input signal into a sigma-delta code. The converter includes a threshold device (222) for generating an output and feedback signal, a filter receiving said analog input signal and said feedback signal from at least one feedback loop. The sigma-delta converter further includes circuits (221, 222) located in said feedback loop for performing a return-to-zero of the sigma-delta code generated by said threshold device at every period of the sigma delta clock, whereby said sigma-delta converter is insensitive to the asymmetry of the rise and fall time of the threshold device. This results in an increase of the signal-to-noise ratio and linearity of the converter, allowing the manufacture of a sigma-delta convertor with discrete components without requiring the development of an integrated circuit using switched capacitor technology.
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