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20 条记录 (耗时 0.019 秒)

    METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT DEVICE
    12.
    发明申请
    METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT DEVICE 失效
    制造集成电路设备的方法

    公开(公告)号：US20120178234A1

    公开(公告)日：2012-07-12

    申请号：US13324035

    申请日：2011-12-13

    申请人： Young-Ho LEE ,  Keon-Soo Kim ,  Seong-Soon Cho ,  Jin-Hyun Shin

    发明人： Young-Ho LEE ,  Keon-Soo Kim ,  Seong-Soon Cho ,  Jin-Hyun Shin

    IPC分类号： H01L21/8239

    CPC分类号： H01L27/0629 ,  H01L27/11531 ,  H01L28/20

    摘要： In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.

    摘要翻译： 在集成电路器件及其制造方法中，电阻器图案位于衬底的器件隔离层上。 电阻器图案包括位于器件隔离层的凹部中的电阻体，以及与电阻体接触并连接在凹部的周围的器件隔离层上的连接器。 连接器具有在上部具有低于电阻体的电阻的金属硅化物图案。 栅极图案位于衬底的有源区上，并且在上部包括金属硅化物图案。 提供电阻器互连以与电阻器图案的连接器接触。 连接器和电阻器互连之间的接触电阻降低。

    Method of forming active region structure
    13.
    发明授权
    Method of forming active region structure 有权
    形成有源区结构的方法

    公开(公告)号：US08187935B2

    公开(公告)日：2012-05-29

    申请号：US12795025

    申请日：2010-06-07

    申请人： Young-Ho Lee ,  Keon-Soo Kim ,  Jae-Hwang Sim ,  Jin-Hyun Shin ,  Kyung-Hoon Min

    发明人： Young-Ho Lee ,  Keon-Soo Kim ,  Jae-Hwang Sim ,  Jin-Hyun Shin ,  Kyung-Hoon Min

    IPC分类号： H01L21/8247

    CPC分类号： H01L21/76229 ,  H01L21/823481 ,  H01L27/1052

    摘要： A method of forming an active region structure includes preparing a semiconductor substrate having a cell array region and a peripheral circuit region, forming upper cell mask patterns having a line shape in the cell array region, forming first and second peripheral mask patterns in the peripheral circuit region, the first and second peripheral mask patterns being stacked in sequence and covering the peripheral circuit region, and upper surfaces of the upper cell mask patterns forming a step difference with an upper surface of the second peripheral mask pattern, forming spacers on sidewalls of the upper cell mask patterns to expose lower portions of the upper cell mask patterns and the second peripheral mask pattern, and removing the lower portions of the upper cell mask patterns using the spacers and the first and second peripheral mask patterns as an etch mask.

    摘要翻译： 形成有源区域结构的方法包括制备具有单元阵列区域和外围电路区域的半导体衬底，在单元阵列区域中形成具有线状的上层单元掩模图案，在外围电路中形成第一和第二外围掩模图案 区域，第一外围掩模图案和第二外围掩模图案依次堆叠并覆盖外围电路区域，并且上部单元掩模图案的上表面与第二外围掩模图案的上表面形成阶梯差，在第二外围掩模图案的侧壁上形成间隔物 上部单元掩模图案以暴露上部单元掩模图案和第二外围掩模图案的下部，并且使用间隔件和第一外围掩模图案和第二外围掩模图案作为蚀刻掩模去除上部单元掩模图案的下部。

    Trench isolated integrated circuit devices including grooves
    15.
    发明授权
    Trench isolated integrated circuit devices including grooves 有权
    沟槽隔离集成电路器件包括沟槽

    公开(公告)号：US07518210B2

    公开(公告)日：2009-04-14

    申请号：US11046965

    申请日：2005-01-31

    申请人： Jae-Sun Yun ,  Jin-Hyun Shin

    发明人： Jae-Sun Yun ,  Jin-Hyun Shin

    IPC分类号： H01L29/02

    CPC分类号： H01L21/76224

    摘要： Trench isolated integrated circuit devices are fabricated by forming a trench including sidewalls in an integrated circuit substrate, and forming a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is formed on the lower device isolation layer and in the grooves. Trench isolated integrated circuit devices include an integrated circuit substrate including a trench having sidewalls and a lower device isolation layer in the trench and extending onto the trench sidewalls. The lower device isolation layer includes grooves therein, a respective one of which extends along a respective one of the sidewalls. An upper device isolation layer is provided on the lower device isolation layer and in the grooves.

    摘要翻译： 沟槽隔离集成电路器件通过在集成电路衬底中形成包括侧壁的沟槽并在沟槽中形成下延伸到沟槽侧壁上的下部器件隔离层来制造。 下部器件隔离层在其中包括凹槽，其相应的一个沿相应的一个侧壁延伸。 上部器件隔离层形成在下部器件隔离层和沟槽中。 沟槽隔离集成电路器件包括集成电路衬底，其包括具有侧壁的沟槽和沟槽中的下部器件隔离层并且延伸到沟槽侧壁上。 下部器件隔离层在其中包括凹槽，其相应的一个沿相应的一个侧壁延伸。 上部器件隔离层设置在下部器件隔离层和沟槽中。

    METHOD OF FORMING ACTIVE REGION STRUCTURE
    17.
    发明申请
    METHOD OF FORMING ACTIVE REGION STRUCTURE 有权
    形成活动区域结构的方法

    公开(公告)号：US20110092048A1

    公开(公告)日：2011-04-21

    申请号：US12795025

    申请日：2010-06-07

    申请人： Young-Ho Lee ,  Keon-Soo Kim ,  Jae-Hwang Sim ,  Jin-Hyun Shin ,  Kyung-Hoon Min

    发明人： Young-Ho Lee ,  Keon-Soo Kim ,  Jae-Hwang Sim ,  Jin-Hyun Shin ,  Kyung-Hoon Min

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76229 ,  H01L21/823481 ,  H01L27/1052

    摘要： A method of forming an active region structure includes preparing a semiconductor substrate having a cell array region and a peripheral circuit region, forming upper cell mask patterns having a line shape in the cell array region, forming first and second peripheral mask patterns in the peripheral circuit region, the first and second peripheral mask patterns being stacked in sequence and covering the peripheral circuit region, and upper surfaces of the upper cell mask patterns forming a step difference with an upper surface of the second peripheral mask pattern, forming spacers on sidewalls of the upper cell mask patterns to expose lower portions of the upper cell mask patterns and the second peripheral mask pattern, and removing the lower portions of the upper cell mask patterns using the spacers and the first and second peripheral mask patterns as an etch mask.

    摘要翻译： 形成有源区域结构的方法包括制备具有单元阵列区域和外围电路区域的半导体衬底，在单元阵列区域中形成具有线状的上层单元掩模图案，在外围电路中形成第一和第二外围掩模图案 区域，第一外围掩模图案和第二外围掩模图案依次堆叠并覆盖外围电路区域，并且上部单元掩模图案的上表面与第二外围掩模图案的上表面形成阶梯差，在第二外围掩模图案的侧壁上形成间隔物 上部单元掩模图案以暴露上部单元掩模图案和第二外围掩模图案的下部，并且使用间隔件和第一外围掩模图案和第二外围掩模图案作为蚀刻掩模去除上部单元掩模图案的下部。

    Methods of fabricating flash memory devices having a sloped trench isolation structure
    18.
    发明授权
    Methods of fabricating flash memory devices having a sloped trench isolation structure 有权
    制造具有倾斜沟槽隔离结构的闪存器件的方法

    公开(公告)号：US07494868B2

    公开(公告)日：2009-02-24

    申请号：US11170467

    申请日：2005-06-29

    申请人： Jeong-hyuk Choi ,  Wang-chul Shin ,  Jin-hyun Shin

    发明人： Jeong-hyuk Choi ,  Wang-chul Shin ,  Jin-hyun Shin

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A method of fabricating a flash memory device. Parallel mask patterns are formed on a substrate. The substrate is etched using the mask patterns to form trenches. An insulating layer pattern is formed in the trenches and an area between the mask patterns. The mask patterns are removed to expose an upper sidewall of the insulating layer pattern that protrudes away from a top surface of the substrate. The insulating layer pattern is isotropically etched to form sloped sidewalls that protrude away from the top surface of the substrate.

    摘要翻译： 一种制造闪速存储器件的方法。 在基板上形成平行的掩膜图案。 使用掩模图案蚀刻衬底以形成沟槽。 在沟槽中形成绝缘层图案和掩模图案之间的区域。 去除掩模图案以暴露远离基板的顶表面突出的绝缘层图案的上侧壁。 绝缘层图案被各向同性地蚀刻以形成从衬底顶表面突出的倾斜侧壁。

    Non-volatile memory devices having floating gates and related methods of forming the same
    19.
    发明申请
    Non-volatile memory devices having floating gates and related methods of forming the same 失效
    具有浮动栅极的非易失性存储器件及其相关方法

    公开(公告)号：US20070108498A1

    公开(公告)日：2007-05-17

    申请号：US11594327

    申请日：2006-11-08

    申请人： Joon-Hee Lee ,  Jong-Ho Park ,  Jin-Hyun Shin ,  Sung-Hoi Hur ,  Yong-Seok Kim ,  Jong-Won Kim

    发明人： Joon-Hee Lee ,  Jong-Ho Park ,  Jin-Hyun Shin ,  Sung-Hoi Hur ,  Yong-Seok Kim ,  Jong-Won Kim

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    摘要： A nonvolatile memory device may include a substrate having a cell region, and a cell device isolation layer on the cell region of the substrate to define a cell active region. A floating gate may include a lower floating gate and an upper floating gate sequentially stacked on the cell active region, and a tunnel insulation pattern may be between the floating gate and the cell active region. A control gate electrode may be on the floating gate, and a blocking insulation pattern may be between the control gate electrode and the floating gate. More particularly, the upper floating gate may include a flat portion on the lower floating gate and a pair of wall portions extending upward from both edges of the flat portion adjacent to the cell device isolation layer. Moreover, a width of an upper portion of a space surrounded by the flat portion and the pair of wall portions may be larger than a width of a lower portion of the space. Related methods are also discussed.

    摘要翻译： 非易失性存储器件可以包括具有单元区域的衬底和在衬底的单元区域上的单元器件隔离层，以限定电池活性区域。 浮置栅极可以包括顺序堆叠在单元有源区上的下浮置栅极和上浮置栅极，并且隧道绝缘图案可以在浮栅和电池有源区之间。 控制栅极电极可以在浮置栅极上，并且阻挡绝缘图案可以在控制栅电极和浮栅之间。 更具体地说，上部浮动栅极可以包括在下部浮动栅极上的平坦部分和从邻近电池器件隔离层的平坦部分的两个边缘向上延伸的一对壁部分。 此外，由平坦部分和一对壁部分围绕的空间的上部的宽度可以大于空间的下部的宽度。 还讨论了相关方法。