公开(公告)号：US08035200B2

公开(公告)日：2011-10-11

申请号：US12792837

申请日：2010-06-03

申请人： John M. Aitken ,  Ethan Harrison Cannon ,  Alvin Wayne Strong

发明人： John M. Aitken ,  Ethan Harrison Cannon ,  Alvin Wayne Strong

IPC分类号： H01L29/786 ,  H01L23/62 ,  H01L23/58 ,  H01L27/12

CPC分类号： H01L21/743 ,  H01L21/76275

摘要： A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped region in direct physical contact with the semiconductor layer; and a device layer on and in direct physical contact with the charge accumulation layer. The charge accumulation layer includes trapped charges of a first sign. The doped region and the semiconductor layer forms a P−N junction diode. The P−N junction diode includes free charges of a second sign opposite to the first sign. The trapped charge in the charge accumulation layer exceeds a preset limit above which semiconductor structure is configured to malfunction. A first voltage is applied to the doped region. A second voltage is applied to the semiconductor layer. A third voltage is applied to the device layer. The third voltage exceeds the first voltage and the second voltage.

摘要翻译： 半导体结构。 半导体结构包括半导体层，在半导体层顶部的电荷累积层，与半导体层直接物理接触的掺杂区域; 以及与电荷累积层直接物理接触的器件层。 电荷累积层包括第一符号的俘获电荷。 掺杂区域和半导体层形成P-N结二极管。 P-N结二极管包括与第一个符号相反的第二个符号的免费电荷。 电荷累积层中的俘获电荷超过预设极限，超过该限制，半导体结构被配置为故障。 第一电压被施加到掺杂区域。 向半导体层施加第二电压。 第三电压被施加到器件层。 第三电压超过第一电压和第二电压。

公开(公告)号：US07943482B2

公开(公告)日：2011-05-17

申请号：US12186762

申请日：2008-08-06

申请人： John M. Aitken ,  Ethan H. Cannon

发明人： John M. Aitken ,  Ethan H. Cannon

IPC分类号： H01L21/76 ,  G06F17/50

CPC分类号： H01L23/556 ,  H01L21/76283 ,  H01L23/481 ,  H01L23/585 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/00

摘要： A design structure is provided for a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The device includes a first structure and a second structure. The first structure includes: a radiation hardened BOX layer under an active device layer; radiation hardened shallow trench isolation (STI) structures between active regions of the active device layer and above the radiation hardened BOX layer; metal interconnects in one or more interlevel dielectric layers above gates structures of the active regions. The second structure is bonded to the first structure. The second structure includes: a Si based substrate; a BOX layer on the substrate; a Si layer with active regions on the BOX; oxide filled STI structures between the active regions of the Si layer; and metal interconnects in one or more interlevel dielectric layers above gates structures. At least one metal interconnect is electrically connecting the first structure to the second structure.

摘要翻译： 提供了一种在SOI技术中具有辐射硬化掩埋绝缘体和隔离绝缘体的半导体器件的设计结构。 该装置包括第一结构和第二结构。 第一结构包括：有源器件层下方的辐射硬化BOX层; 在有源器件层的有源区和辐射硬化BOX层之上的辐射硬化浅沟槽隔离（STI）结构; 在有源区域的栅极结构之上的一个或多个层间电介质层中的金属互连。 第二结构被结合到第一结构。 第二结构包括：基于硅的衬底; 衬底上的BOX层; BOX上有活性区的Si层; 在Si层的有源区之间的氧化物填充的STI结构; 以及栅极结构之上的一个或多个层间电介质层中的金属互连。 至少一个金属互连件将第一结构电连接到第二结构。

公开(公告)号：US07791169B2

公开(公告)日：2010-09-07

申请号：US12105395

申请日：2008-04-18

申请人： John M. Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

发明人： John M. Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

IPC分类号： H01L29/76

CPC分类号： H01L27/1203 ,  H01L29/92

摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.

摘要翻译： 公开了一种包含用于降低结构内的器件的软错误率的电容器的半导体结构。 多层半导体结构包括通过有源硅层，第一绝缘体层和第一体层形成并延伸到第二绝缘体层的绝缘体填充的深沟槽隔离结构。 所形成的第一体层的隔离部分限定第一电容器板。 与第一电容器板相邻的第二绝缘体层的一部分用作电容器电介质。 硅衬底或由第三绝缘体层和另一个深沟槽隔离结构隔离的第二体层的一部分可以用作第二电容器板。 第一电容器触点直接地或经由线阵列将第一电容器板耦合到器件的电路节点，以便增加电路节点的临界电荷Qcrit。

公开(公告)号：US20100035393A1

公开(公告)日：2010-02-11

申请号：US12186750

申请日：2008-08-06

申请人： John M. Aitken ,  Ethan H. Cannon

发明人： John M. Aitken ,  Ethan H. Cannon

IPC分类号： H01L21/8238 ,  H01L21/76

CPC分类号： H01L27/0688 ,  H01L21/2007 ,  H01L21/76264 ,  H01L21/8221 ,  H01L21/84

摘要： A method is provided for fabricating a semiconductor device and more particularly to a method of manufacturing a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The method includes removing a substrate from an SOI wafer and selectively removing a buried oxide layer formed as a layer between the SOI wafer and active regions of a device. The method further comprises selectively removing isolation oxide formed between the active regions, and replacing the removed buried oxide layer and the isolation oxide with radiation hardened insulators.

摘要翻译： 提供一种用于制造半导体器件的方法，更具体地说，涉及在SOI技术中制造具有辐射硬化掩埋绝缘体和隔离绝缘体的半导体器件的方法。 该方法包括从SOI晶片去除衬底并选择性地去除在SOI晶片和器件的有源区之间形成为层的掩埋氧化物层。 该方法还包括选择性地去除在有源区之间形成的隔离氧化物，并用辐射硬化绝缘体代替去除的掩埋氧化物层和隔离氧化物。

公开(公告)号：US20080197337A1

公开(公告)日：2008-08-21

申请号：US12109085

申请日：2008-04-24

申请人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

发明人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

IPC分类号： H01L47/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/18 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145

摘要： The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.

摘要翻译： 本发明涉及诸如ROM或EPROM的非易失性存储器，其中存储器的信息密度相对于包括两个逻辑状态器件的常规非易失性存储器而增加。 具体地，本发明的非易失性存储器包括嵌入在热导率为约1W / m-K以下的材料中的SiN / TaN / SiN薄膜电阻器; 以及耦合到电阻器的非线性含Si器件。 读写电路和操作也在本申请中提供。

公开(公告)号：US20080191314A1

公开(公告)日：2008-08-14

申请号：US12105395

申请日：2008-04-18

申请人： John M. Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

发明人： John M. Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

IPC分类号： H01L27/108

CPC分类号： H01L27/1203 ,  H01L29/92

摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.

摘要翻译： 公开了一种包含用于降低结构内的器件的软错误率的电容器的半导体结构。 多层半导体结构包括通过有源硅层，第一绝缘体层和第一体层形成并延伸到第二绝缘体层的绝缘体填充的深沟槽隔离结构。 所形成的第一体层的隔离部分限定第一电容器板。 与第一电容器板相邻的第二绝缘体层的一部分用作电容器电介质。 硅衬底或由第三绝缘体层和另一个深沟槽隔离结构隔离的第二体层的一部分可以用作第二电容器板。 第一电容器触点直接地或经由线阵列将第一电容器板耦合到器件的电路节点，以便增加电路节点的临界电荷Qcrit。

公开(公告)号：US07388274B2

公开(公告)日：2008-06-17

申请号：US11838931

申请日：2007-08-15

申请人： John M. Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

发明人： John M. Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

IPC分类号： H01L29/00 ,  H01L29/76

CPC分类号： H01L27/1203 ,  H01L29/92

摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.

公开(公告)号：US07381981B2

公开(公告)日：2008-06-03

申请号：US11161332

申请日：2005-07-29

申请人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

发明人： John M. Aitken ,  Fen Chen ,  Kai D. Feng

IPC分类号： H01L29/02 ,  H01L47/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/18 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145

摘要： The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.

摘要翻译： 本发明涉及诸如ROM或EPROM的非易失性存储器，其中存储器的信息密度相对于包括两个逻辑状态器件的常规非易失性存储器而增加。 具体地，本发明的非易失性存储器包括嵌入在热导率为约1W / m-K以下的材料中的SiN / TaN / SiN薄膜电阻器; 以及耦合到电阻器的非线性含Si器件。 读写电路和操作也在本申请中提供。

公开(公告)号：US06333239B1

公开(公告)日：2001-12-25

申请号：US09532811

申请日：2000-03-21

申请人： John M. Aitken ,  Alvin W. Strong

发明人： John M. Aitken ,  Alvin W. Strong

IPC分类号： H01L2120

CPC分类号： H01L28/91

摘要： A planarized interleaved capacitor for use with a substrate. The capacitor has a plurality of planarized metal layers formed above the substrate, at least one dielectric layer disposed between the plurality of planarized metal layers, and at least one insulator layer disposed over one of the plurality of metal layers.

摘要翻译： 用于衬底的平面化交错电容器。 所述电容器具有形成在所述基板上方的多个平坦化的金属层，设置在所述多个平坦化金属层之间的至少一个电介质层以及设置在所述多个金属层之一上的至少一个绝缘体层。

公开(公告)号：US5530290A

公开(公告)日：1996-06-25

申请号：US226103

申请日：1994-04-11

申请人： John M. Aitken ,  Klaus D. Beyer ,  Billy L. Crowder ,  Stephen E. Greco

发明人： John M. Aitken ,  Klaus D. Beyer ,  Billy L. Crowder ,  Stephen E. Greco

IPC分类号： H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002

摘要： Fabrication methods for forming a network of walls concurrently with the formation of studs for interconnecting plural device layers of a large scale integrated circuit device permits aggressive reduction of the average dielectric constant of air dielectric structures. Wall sections may be positioned to laterally support high aspect ratio connecting studs with a network of open or closed polygons. Wall patterns may also be open from layer to layer to allow formation of large scale air dielectric structures over a plurality of layers in a single material removal step. A wide range of shear strengths and reductions of average dielectric constant can be achieved even within a single device layer of a large scale integrated circuit and exploited to meet circuit design and device fabrication process requirements.

摘要翻译： 用于形成用于互连大规模集成电路器件的多个器件层的螺柱的壁的形成网络的制造方法允许大大降低空气电介质结构的平均介电常数。 壁部分可以被定位成横向支撑具有开放或闭合多边形网络的高纵横比连接螺柱。 壁图案也可以从一层开放，以允许在单个材料去除步骤中在多个层上形成大规模空气介电结构。 即使在大规模集成电路的单个器件层内，也可以获得宽范围的剪切强度和平均介电常数的降低，并被用于满足电路设计和器件制造工艺要求。