公开(公告)号：US08407488B2

公开(公告)日：2013-03-26

申请号：US13091882

申请日：2011-04-21

Applicant: Makoto Fujiwara ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

Inventor： Makoto Fujiwara ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

IPC: G06F12/14 ,  H04L9/00

CPC classification number: G06F21/72 ,  G06F9/4401 ,  G06F21/123 ,  G06F21/85 ,  G06F2221/2105

Abstract: A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.

公开(公告)号：US07852777B2

公开(公告)日：2010-12-14

申请号：US11515768

申请日：2006-09-06

Applicant: Toshihiko Maruoka ,  Tsukasa Yoshiura ,  Junichi Yasui

Inventor： Toshihiko Maruoka ,  Tsukasa Yoshiura ,  Junichi Yasui

IPC: H04L12/28

CPC classification number: G06F13/385

Abstract: A network hardware device of the invention includes a reception section receiving data from a network, and outputting a reception completion signal, a timer section measuring a preset time, and a delay section generating an interrupt signal so as to notify a host CPU of completion of the reception. When the timer section does not measure a time, the delay section generates an interrupt signal upon reception of the reception completion signal. On the other hand, when the timer section measures a time, upon reception of the reception completion signal, the delay section generates an interrupt signal after the timer section measures a preset time.

Abstract translation: 本发明的网络硬件装置包括从网络接收数据并输出接收完成信号的接收部分，测量预设时间的定时器部分和产生中断信号的延迟部分，以通知主机CPU完成 接待处。 当定时器部分不测量时间时，延迟部分在接收到接收完成信号时产生中断信号。 另一方面，当定时器部分测量时间时，在接收到接收完成信号之后，延迟部分在定时器部分测量预设时间之后产生中断信号。

公开(公告)号：US07831841B2

公开(公告)日：2010-11-09

申请号：US12010132

申请日：2008-01-22

Applicant: Makoto Fujiwara ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

Inventor： Makoto Fujiwara ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

IPC: G06F12/14

CPC classification number: G06F21/72 ,  G06F9/4401 ,  G06F21/123 ,  G06F21/85 ,  G06F2221/2105

Abstract: A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.

Abstract translation: 安全LSI装置1包括用于加密程序的加密部分2和用于从外部存储器100输入/输出程序或数据的外部I / F50。在加密部分2中，私钥的操作 关于执行由密钥生成/更新排序器30确定的序列是不允许的，算术处理部分20被禁止。 在外部I / F50中，程序处理部51和数据处理部55彼此独立地构成。

公开(公告)号：US20080144818A1

公开(公告)日：2008-06-19

申请号：US12010132

申请日：2008-01-22

Applicant: Makoto Fujiwara ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

Inventor： Makoto Fujiwara ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

IPC: H04L9/00

CPC classification number: G06F21/72 ,  G06F9/4401 ,  G06F21/123 ,  G06F21/85 ,  G06F2221/2105

Abstract: A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.

Abstract translation: 安全LSI装置1包括用于加密程序的加密部分2和用于从/向外部存储器100输入/输出程序或数据的外部I / F 50。 在加密部分2中，禁止私钥运算处理部分20的执行由密钥生成/更新定序器30确定的序列是不允许的。 在外部I / F50中，程序处理部51和数据处理部55彼此独立地构成。

公开(公告)号：US20070217614A1

公开(公告)日：2007-09-20

申请号：US11798367

申请日：2007-05-14

Applicant: Makoto Fujiwara ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

Inventor： Makoto Fujiwara ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

IPC: H04L9/00

CPC classification number: G06F21/123 ,  G06F21/572 ,  G06F21/72

Abstract: A system including a secure LSI 1 establishes a communication path to/from a server 3 (UD1), and receives a common key-encrypted program generated by encryption with a common key and transmitted from the server 3 (UD6 and UD7). The received common key-encrypted program is decrypted to generate a raw program, and the raw program is re-encrypted with an inherent key to newly generate an inherent key-encrypted program, which is stored in an external memory.

Abstract translation: 包括安全LSI1的系统建立到服务器3（UD 1）的通信路径，并且从服务器3（UD 6和UD 7）接收通过公共密钥通过加密生成的公共密钥加密程序， 。 对所接收的公用密钥加密程序进行解密以生成原始程序，并且用固有密钥重新加密原始程序，以新生成存储在外部存储器中的固有密钥加密程序。

公开(公告)号：US20050141534A1

公开(公告)日：2005-06-30

申请号：US10986465

申请日：2004-11-12

Applicant: Manabu Kawabata ,  Junichi Yasui

Inventor： Manabu Kawabata ,  Junichi Yasui

IPC: H04L12/951 ,  H04L12/28 ,  H04L12/56

CPC classification number: H04L12/56

Abstract: Packet processing method and device. The device includes: a storage device for storing data; a transfer device for dividing the data into a plurality of data with a predetermined length and arranging the divided data at intervals in the storage device while securing a first blank area for attaching a protocol header to the divided data and a second blank area for attaching a protocol footer to the divided area; a read address control device for implementing access of data arranged at intervals in the storage device as continuous data; and a write address control device for storing the protocol header to be attached in the first blank area and the protocol footer to be attached in the second blank area when the packet conversion processing is performed on the divided data.

Abstract translation: 数据包处理方法和设备。 该装置包括：用于存储数据的存储装置; 用于将数据分割成具有预定长度的多个数据的传送装置，并且在将用于附加协议头部的第一空白区域固定到划分的数据的同时，将分割的数据间隔地布置在存储装置中，以及第二空白区域用于附加 协议页脚到分区; 读取地址控制装置，用于实现以存储装置间隔排列的数据的访问作为连续数据; 以及写入地址控制装置，用于当对划分的数据进行分组转换处理时，存储要附加在第一空白区域中的协议头部和要附着在第二空白区域中的协议页脚。

公开(公告)号：US20130151836A1

公开(公告)日：2013-06-13

申请号：US13761964

申请日：2013-02-07

Applicant: Makoto FUJIWARA ,  Yusuke NEMOTO ,  Junichi YASUI ,  Takuji MAEDA ,  Takayuki ITO ,  Yasushi YAMADA ,  Shinji INOUE

Inventor： Makoto FUJIWARA ,  Yusuke NEMOTO ,  Junichi YASUI ,  Takuji MAEDA ,  Takayuki ITO ,  Yasushi YAMADA ,  Shinji INOUE

IPC: G06F9/44

CPC classification number: G06F21/72 ,  G06F9/4401 ,  G06F21/123 ,  G06F21/85 ,  G06F2221/2105

Abstract: A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.

Abstract translation: 安全LSI装置1包括用于加密程序的加密部分2和用于从外部存储器100输入/输出程序或数据的外部I / F50。在加密部分2中，私钥的操作 关于执行由密钥生成/更新排序器30确定的序列是不允许的，算术处理部分20被禁止。 在外部I / F50中，程序处理部51和数据处理部55彼此独立地构成。

公开(公告)号：US08122262B2

公开(公告)日：2012-02-21

申请号：US12877615

申请日：2010-09-08

Applicant: Makoto Fujiwara ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

Inventor： Makoto Fujiwara ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

IPC: G06F12/14

CPC classification number: G06F21/72 ,  G06F9/4401 ,  G06F21/123 ,  G06F21/85 ,  G06F2221/2105

Abstract: A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.

Abstract translation: 安全LSI装置1包括用于加密程序的加密部分2和用于从外部存储器100输入/输出程序或数据的外部I / F50。在加密部分2中，私钥的操作 关于执行由密钥生成/更新排序器30确定的序列是不允许的，算术处理部分20被禁止。 在外部I / F50中，程序处理部51和数据处理部55彼此独立地构成。

公开(公告)号：US20110202752A1

公开(公告)日：2011-08-18

申请号：US13091882

申请日：2011-04-21

Applicant: Makoto FUJIWARA ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

Inventor： Makoto FUJIWARA ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

IPC: G06F9/00 ,  G06F12/14

CPC classification number: G06F21/72 ,  G06F9/4401 ,  G06F21/123 ,  G06F21/85 ,  G06F2221/2105

Abstract: A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.

Abstract translation: 安全LSI装置1包括用于加密程序的加密部分2和用于从外部存储器100输入/输出程序或数据的外部I / F50。在加密部分2中，私钥的操作 关于执行由密钥生成/更新排序器30确定的序列是不允许的，算术处理部分20被禁止。 在外部I / F50中，程序处理部51和数据处理部55彼此独立地构成。

公开(公告)号：US20100329456A1

公开(公告)日：2010-12-30

申请号：US12877615

申请日：2010-09-08

Applicant: Makoto FUJIWARA ,  Yusuke NEMOTO ,  Junichi YASUI ,  Takuji MAEDA ,  Takayuki ITO ,  Yasushi YAMADA ,  Shinji INOUE

Inventor： Makoto FUJIWARA ,  Yusuke NEMOTO ,  Junichi YASUI ,  Takuji MAEDA ,  Takayuki ITO ,  Yasushi YAMADA ,  Shinji INOUE

IPC: H04L9/14 ,  H04L9/00

CPC classification number: G06F21/72 ,  G06F9/4401 ,  G06F21/123 ,  G06F21/85 ,  G06F2221/2105

Abstract: A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.

Abstract translation: 安全LSI装置1包括用于加密程序的加密部分2和用于从外部存储器100输入/输出程序或数据的外部I / F50。在加密部分2中，私钥的操作 关于执行由密钥生成/更新排序器30确定的序列是不允许的，算术处理部分20被禁止。 在外部I / F50中，程序处理部51和数据处理部55彼此独立地构成。