公开(公告)号：US06489832B1

公开(公告)日：2002-12-03

申请号：US09672444

申请日：2000-09-29

申请人： Tae-hyun Kim ,  Kye-hyun Kyung ,  Kyu-han Han ,  Dong-hak Seen

发明人： Tae-hyun Kim ,  Kye-hyun Kyung ,  Kyu-han Han ,  Dong-hak Seen

IPC分类号： H01H8500

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A chip information output circuit including a fuse box, capable of reducing a layout area without affecting input capacitance, is provided. The chip information output circuit includes a plurality of fuse blocks for generating different outputs according to whether a fuse is cut and a pipeline circuit for receiving a plurality of signals, which are output in parallel from the respective fuse blocks, and serially outputting the plurality of signals. Each of the fuse blocks includes a plurality of fuse boxes for generating output signals, the levels of which are either a high or low logic level according to whether the fuses included therein are cut, wherein the respective fuse boxes are enabled in response to the respective control signals and the output lines of the fuse boxes are wired by an OR operation. The pipeline circuit includes a plurality of serially connected latch units for latching signals output from the fuse blocks and outputting the latched signals.

摘要翻译： 提供一种芯片信息输出电路，其包括能够减小布局面积而不影响输入电容的保险丝盒。 芯片信息输出电路包括多个熔丝块，用于根据熔丝被切断产生不同的输出，以及一个流水线电路，用于接收从各个熔丝块并行输出的多个信号，并串行输出多个 信号。 每个熔丝块包括用于产生输出信号的多个熔丝盒，根据其中包括的保险丝是否被切断，其电平是高或低逻辑电平，其中相应的熔丝盒响应于相应的 保险丝盒的控制信号和输出线通过OR操作进行接线。 管线电路包括多个串联的锁存单元，用于锁存从熔丝块输出的信号并输出​​锁存信号。

公开(公告)号：US06486651B1

公开(公告)日：2002-11-26

申请号：US09721135

申请日：2000-11-22

申请人： Jong-soo Lee ,  Kye-hyun Kyung ,  Dae-sun Kim ,  Hyo-jin Oh ,  Sang-chul Kim ,  Tae-seek Son

发明人： Jong-soo Lee ,  Kye-hyun Kyung ,  Dae-sun Kim ,  Hyo-jin Oh ,  Sang-chul Kim ,  Tae-seek Son

IPC分类号： G01R2312

CPC分类号： G11C29/12015 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/14

摘要： Integrated circuit devices and methods of operating same include a delayed locked loop (DLL) circuit that can be operated at a high frequency during a normal operation mode and during a test mode. The test mode may be, for example, for performing burn-in testing. For example, an integrated circuit device may include a DLL control circuit that generates a control signal that is responsive to a test mode signal. An oscillator circuit may generate a clock signal that is responsive to the test mode signal. This clock signal may be a high frequency clock signal, such as that used to drive a DLL circuit during a normal operation mode. A DLL circuit, which is responsive to the clock signal, may be configured to operate in either a test mode or a normal operation mode based on the control signal. By generating the clock signal at a high frequency, the DLL circuit may be evaluated during burn-in testing, for example, under conditions that are comparable to conditions during normal operation.

摘要翻译： 集成电路装置及其操作方法包括可以在正常操作模式期间和在测试模式期间以高频率操作的延迟锁定环（DLL）电路。 测试模式可以是例如用于进行老化测试。 例如，集成电路装置可以包括产生响应于测试模式信号的控制信号的DLL控制电路。 振荡器电路可以产生响应于测试模式信号的时钟信号。 该时钟信号可以是高频时钟信号，例如用于在正常操作模式期间驱动DLL电路的时钟信号。 响应于时钟信号的DLL电路可以被配置为基于控制信号在测试模式或正常操作模式中操作。 通过以高频产生时钟信号，可以在老化测试期间评估DLL电路，例如在与正常操作期间的条件相当的条件下。

公开(公告)号：US06438015B1

公开(公告)日：2002-08-20

申请号：US09829803

申请日：2001-04-10

申请人： Kye-hyun Kyung

发明人： Kye-hyun Kyung

IPC分类号： G11C506

摘要： Disclosed is a memory device, comprising a memory controller, a clock input pin for receiving a clock signal, a first chip selection signal input pin for receiving a first chip selection signal for a row address strobe from the memory controller, a second chip selection signal input pin for receiving a second chip selection signal for a column address strobe from the memory controller, a row command input pin for receiving a row command from the memory controller, a column command input pin for receiving a column command from the memory controller, a plurality of row address input pins for receiving row addresses from the memory controller, and a plurality of column address input pins for receiving column addresses from the memory controller.

公开(公告)号：USRE37753E1

公开(公告)日：2002-06-18

申请号：US09726665

申请日：2000-11-29

申请人： Kye-Hyun Kyung

发明人： Kye-Hyun Kyung

IPC分类号： G11C800

CPC分类号： G11C7/1093 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22

摘要： A semiconductor memory device includes input/output circuitry capable of operating in sync with an externally provided I/O clock signal. A data in buffer and a data out buffer provide for serial to parallel conversion of write data and, conversely, parallel to serial conversion of read data. The data buffers can be synchronized with the external I/O clock signal thereby decoupling their operation from the internal system clock signal. This strategy improves I/O bandwidth and further provides for matching different numbers of bit lines or word sizes as between the I/O data port and the memory array itself. An internal I/O clock generator can be provided for generating I/O clock signals, again without the limitation of synchronizing to the internal system clock signal.

摘要翻译： 半导体存储器件包括能够与外部提供的I / O时钟信号同步操作的输入/输出电路。 缓冲器和数据输出缓冲器中的数据提供写入数据的串行到并行转换，相反地，并行读取数据的串行转换。 数据缓冲器可以与外部I / O时钟信号同步，从而将其操作与内部系统时钟信号分离。 该策略提高了I / O带宽，并进一步提供了在I / O数据端口和存储器阵列本身之间匹配不同数量的位线或字体大小。 可以提供内部I / O时钟发生器，用于产生I / O时钟信号，而不受与内部系统时钟信号同步的限制。

公开(公告)号：US6141271A

公开(公告)日：2000-10-31

申请号：US198704

申请日：1998-11-24

申请人： Sun-byeong Yoon ,  Kye-hyun Kyung

发明人： Sun-byeong Yoon ,  Kye-hyun Kyung

IPC分类号： G01R31/28 ,  G01R31/26 ,  G11C11/401 ,  G11C29/00 ,  G11C29/14 ,  G11C29/48 ,  G11C7/00

CPC分类号： G11C29/48 ,  G11C29/14

摘要： An integrated circuit memory device includes a test mode. Data is written to and read from the integrated circuit memory device in the test mode. The integrated circuit memory device includes a memory array that includes memory cells that store data. A test control circuit generates control signals that control the data read from the memory cells. A data output circuit outputs data read from the memory cells from the integrated circuit memory device in response to the test column address strobe signal. In particular, the test column address strobe signal includes a series of high to low and low to high transitions, wherein the data output circuit outputs data read from the memory cells in response to the series of high to low and low to high transitions. The high to low and low to high transitions of the test column address strobe signal may be used to output the data read from the memory cells, thereby reducing the need for an external test clock signal to be supplied to the integrated circuit memory device during testing.

摘要翻译： 集成电路存储器件包括测试模式。 在测试模式下，数据被写入和读取集成电路存储器件。 集成电路存储器件包括存储器阵列，该存储器阵列包括存储数据的存储器单元。 测试控制电路产生控制从存储器单元读取的数据的控制信号。 数据输出电路响应于测试列地址选通信号，从集成电路存储器件输出从存储器单元读出的数据。 特别地，测试列地址选通信号包括一系列从高到低和低到高的转变，其中数据输出电路响应于一系列从高到低和从低到高的转变输出从存储器单元读出的数据。 可以使用测试列地址选通信号的高到低和从低到高的转变来输出从存储器单元读取的数据，从而减少在测试期间将外部测试时钟信号提供给集成电路存储器件的需要 。

公开(公告)号：US08729615B2

公开(公告)日：2014-05-20

申请号：US13248333

申请日：2011-09-29

申请人： Chang Hyun Lee ,  Young-Woo Park ,  Kye-Hyun Kyung ,  Cheon-An Lee ,  Sung-il Chang ,  Chul Bum Kim

发明人： Chang Hyun Lee ,  Young-Woo Park ,  Kye-Hyun Kyung ,  Cheon-An Lee ,  Sung-il Chang ,  Chul Bum Kim

IPC分类号： H01L27/108

CPC分类号： H01L21/823857 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/105 ,  H01L27/11546 ,  H01L27/11556

摘要： A semiconductor memory device has a memory cell region and a peripheral region. The device includes low voltage transistors at the peripheral region having gate insulation films with different thicknesses. For example, a gate insulation film of a low voltage transistor used in an input/output circuit of the memory device may be thinner than the gate insulation film of a low voltage transistor used in a core circuit for the memory device. Since low voltage transistors used at an input/output circuit are formed to be different from low voltage transistors used at a core circuit or a high voltage pump circuit, high speed operation and low power consumption characteristics of a non-volatile memory device may be.

摘要翻译： 半导体存储器件具有存储单元区域和周边区域。 该器件包括具有不同厚度的栅极绝缘膜的外围区域的低电压晶体管。 例如，在存储器件的输入/输出电路中使用的低电压晶体管的栅极绝缘膜可以比用于存储器件的核心电路中的低电压晶体管的栅极绝缘膜更薄。 由于在输入/输出电路中使用的低压晶体管形成为与核心电路或高压泵浦电路所使用的低压晶体管不同，所以可以是非易失性存储器件的高速工作和低功耗特性。

公开(公告)号：US08477546B2

公开(公告)日：2013-07-02

申请号：US12656430

申请日：2010-01-29

申请人： Kye-hyun Kyung

发明人： Kye-hyun Kyung

IPC分类号： G11C7/00

CPC分类号： G11C29/808

摘要： A semiconductor memory device includes a plurality of memory areas. Each of the memory areas includes a normal cell array and a redundancy cell array for repairing defective cells generated in the normal cell array such that the semiconductor memory device is usable even when memory arrays include defective cells. A size of a redundancy cell array of a first memory area is greater than a size of the redundancy cell arrays of the other memory areas.

摘要翻译： 半导体存储器件包括多个存储区域。 每个存储区域包括正常单元阵列和用于修复在正常单元阵列中产生的有缺陷单元的冗余单元阵列，使得半导体存储器件即使当存储器阵列包括有缺陷单元时也是可用的。 第一存储区域的冗余单元阵列的大小大于其他存储区域的冗余单元阵列的大小。

公开(公告)号：US20120221880A1

公开(公告)日：2012-08-30

申请号：US13396618

申请日：2012-02-15

申请人： BO-GEUN KIM ,  Kye-hyun Kyung ,  Jae-yong Jeong ,  Seung-hun Choi ,  Seok-cheon Kwon ,  Chul-ho Lee

发明人： BO-GEUN KIM ,  Kye-hyun Kyung ,  Jae-yong Jeong ,  Seung-hun Choi ,  Seok-cheon Kwon ,  Chul-ho Lee

IPC分类号： G06F1/12

CPC分类号： G06F1/12 ,  G06F1/04 ,  G06F1/14 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0683 ,  G06F13/1689 ,  G11C7/222 ,  Y02D10/14

摘要： A memory system comprises a controller that generates a processor clock, and a plurality of memory devices each comprising an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

摘要翻译： 存储器系统包括产生处理器时钟的控制器和多个存储器件，每个存储器件包括与处理器时钟同步地产生内部时钟的内部时钟发生器，以及与所述处理器时钟同步地执行峰值电流产生操作的存储器 内部时钟，其中至少两个存储器件在不同时间产生它们各自的内部时钟，使得相应的峰值电流产生操作在不同的时间执行。

公开(公告)号：US20120146118A1

公开(公告)日：2012-06-14

申请号：US13248333

申请日：2011-09-29

申请人： Chang-Hyun Lee ,  Young-Woo Park ,  Kye-Hyun Kyung ,  Cheon-An Lee ,  Sung-il Chang ,  Chul Bum Kim

发明人： Chang-Hyun Lee ,  Young-Woo Park ,  Kye-Hyun Kyung ,  Cheon-An Lee ,  Sung-il Chang ,  Chul Bum Kim

IPC分类号： H01L27/108 ,  H01L27/092

CPC分类号： H01L21/823857 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/105 ,  H01L27/11546 ,  H01L27/11556

摘要： A semiconductor memory device has a memory cell region and a peripheral region. The device includes low voltage transistors at the peripheral region having gate insulation films with different thicknesses. For example, a gate insulation film of a low voltage transistor used in an input/output circuit of the memory device may be thinner than the gate insulation film of a low voltage transistor used in a core circuit for the memory device. Since low voltage transistors used at an input/output circuit are formed to be different from low voltage transistors used at a core circuit or a high voltage pump circuit, high speed operation and low power consumption characteristics of a non-volatile memory device may be.

摘要翻译： 半导体存储器件具有存储单元区域和周边区域。 该器件包括具有不同厚度的栅极绝缘膜的外围区域的低电压晶体管。 例如，在存储器件的输入/输出电路中使用的低电压晶体管的栅极绝缘膜可以比用于存储器件的核心电路中的低电压晶体管的栅极绝缘膜更薄。 由于在输入/输出电路中使用的低压晶体管形成为与核心电路或高压泵浦电路所使用的低压晶体管不同，所以可以是非易失性存储器件的高速工作和低功耗特性。

公开(公告)号：US20100054053A1

公开(公告)日：2010-03-04

申请号：US12614826

申请日：2009-11-09

申请人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

发明人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

IPC分类号： G11C7/00

CPC分类号： G11C5/00 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/222 ,  G11C8/06 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4093

摘要： An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data write operation, and the data input/output pins may be further configured to provide data to the memory controller from the memory cell array during a data read operation. A mode register may be configured to store information defining an operational characteristic of the memory device, and the mode register may be configured to be set using the data input/output bus. Related methods, systems, and additional devices are also discussed.

摘要翻译： 集成电路存储器件可以包括存储单元阵列和多个数据输入/输出引脚。 多个数据输入/输出引脚可以被配置为在数据写入操作期间从存储器控制器接收要写入存储单元阵列的数据，并且数据输入/输出引脚还可以被配置为向存储器控制器 在数据读取操作期间从存储单元阵列。 模式寄存器可以被配置为存储定义存储器件的操作特性的信息，并且模式寄存器可以被配置为使用数据输入/输出总线进行设置。 还讨论了相关方法，系统和附加设备。