公开(公告)号：US07984209B1

公开(公告)日：2011-07-19

申请号：US11638150

申请日：2006-12-12

申请人： Vinson Chan ,  Michael Menghui Zheng ,  Chong H. Lee

发明人： Vinson Chan ,  Michael Menghui Zheng ,  Chong H. Lee

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F5/12 ,  G06F2205/126

摘要： Interface circuitry that is used to interface data between two different clock regimes that may have somewhat different speeds includes the ability to determine which of the clock regimes is faster. Depending on which clock regime is found to be faster, the baseline (nominal difference between data write and data read addresses of a FIFO memory in the interface circuitry) is shifted (i.e., toward the full or empty condition of the FIFO, as is appropriate for which of the clock regimes has been found to be faster). Adjustments may also be made to the threshold(s) used for such purposes as character insertion/deletion and overflow/underflow indication. This technique may allow use of a smaller FIFO and reduce latency of the interface circuitry.

摘要翻译： 用于在可能具有一些不同速度的两种不同时钟制式之间对数据进行接口的接口电路包括确定哪个时钟方案更快的能力。 根据哪个时钟状态被发现更快，基线（数据写入和接口电路中的FIFO存储器的数据读取地址之间的标称差）被移位（即，朝向FIFO的满或空状态，如适用的那样） 为什么时钟制度被发现是更快）。 还可以对用于诸如字符插入/删除和溢出/下溢指示的目的的阈值进行调整。 该技术可以允许使用较小的FIFO并减少接口电路的延迟。

公开(公告)号：US07627806B1

公开(公告)日：2009-12-01

申请号：US11436463

申请日：2006-05-17

申请人： Divya Vijayaraghavan ,  Michael Menghui Zheng ,  Chong H. Lee ,  Ning Xue ,  Tam Nguyen

发明人： Divya Vijayaraghavan ,  Michael Menghui Zheng ,  Chong H. Lee ,  Ning Xue ,  Tam Nguyen

IPC分类号： H03M13/09

CPC分类号： H04L1/0052 ,  H03M13/09 ,  H03M13/6516 ,  H04L1/0061

摘要： A programmable logic integrated circuit device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry that is at least partly hard-wired to perform at least some functional aspects of the HSSI operations. Cyclic redundancy check (CRC) generation and/or checking circuitry is now included in this HSSI circuitry, and again, this CRC circuitry is at least partly hard-wired to perform at least some functional aspects of its operations(s).

摘要翻译： 可编程逻辑集成电路器件（“PLD”）包括至少部分硬接线以执行HSSI操作的至少一些功能方面的高速串行接口（“HSSI”）电路。 循环冗余校验（CRC）生成和/或检查电路现在包括在该HSSI电路中，并且再次，该CRC电路至少部分地硬接线以执行其操作的至少一些功能方面。