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11.发明授权公开(公告)号：US12237189B2
公开(公告)日：2025-02-25
申请号：US16688238
申请日：2019-11-19
Applicant: Micron Technology, Inc.
Inventor： Nagasubramaniyan Chandrasekaran
IPC: H01L21/67 , G01N21/95 , H01L21/66 , H01L21/673 , H01L21/677 , H01L21/687
Abstract: A wafer storage device may include one or more mutually aligned rails extending from two opposing side walls, each pair of mutually aligned rails configured to support a wafer between the side walls. The wafer storage device includes one or more sensors coupled to at least some of the one or more rails. The one or more sensors may be configured to detect a physical property of the wafer. The wafer storage device may further include a processor configured to analyze data from the one or more sensors, and a memory device. The memory device may be configured to store data produced by at least the one or more sensors or the processor. The wafer storage device may also include a power storage device configured to receive power from an external source and supply power to the one or more sensors and the processor.
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公开(公告)号：US12237020B2
公开(公告)日：2025-02-25
申请号：US17888298
申请日：2022-08-15
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati
Abstract: Methods, systems, and devices for storing bits, such as N−1 bits, with cells, such as N cells, in a memory device are described. A memory device may generate a first sensing voltage that is based on a first voltage of a first digit line and a second voltage of a second digit line. The memory device may also generate a second sensing voltage that is based on a third voltage of a third digit line and a fourth voltage of a fourth digit line. The memory device may then determine a bit value based at least in part on a difference between the first sensing voltage and the second sensing voltage.
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公开(公告)号：US12237018B2
公开(公告)日：2025-02-25
申请号：US18386919
申请日：2023-11-03
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Robert W. Strong , William Akin , Jeremy Binfet
Abstract: A method includes receiving signaling indicative of performance of a sanitization operation to a processing device coupled to a memory device and applying a sanitization voltage to a plurality of memory blocks of the memory device. The sanitization voltage can be greater than an erase voltage of the plurality of memory blocks.
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公开(公告)号：US12236999B2
公开(公告)日：2025-02-25
申请号：US17830042
申请日：2022-06-01
Applicant: Micron Technology, Inc.
Inventor： Lorenzo Fratin , Fabio Pellizzer , Paolo Fantini
IPC: G11C11/40 , G11C5/06 , G11C11/4074 , G11C11/408 , G11C11/4094
Abstract: Methods, systems, and devices for decoder architectures for three-dimensional memory devices are described. In some cases, a decoder for a memory device may include two portions. A first portion of the decoder may be manufactured on top of the memory array, and may include a pillar decoding portion to selectively bias a first array of decoding elements coupled with conductive pillars of the memory array and a word line decoding portion to selectively bias a second array of decoding elements coupled with word lines of the memory array. A second portion of the decoder may be implemented in a separate semiconductor device which may include a set of logic circuits configured to drive signal to a set of contacts bonded to contacts of the first portion to drive the digit lines, voltage sources, and gate lines.
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公开(公告)号：US12236131B2
公开(公告)日：2025-02-25
申请号：US17386315
申请日：2021-07-27
Applicant: Micron Technology, Inc.
Inventor： Trevor Conrad Meyerowitz , Dhawal Bavishi
Abstract: A first command is scheduled on a command bus, where the first command requires use of a data bus resource at a first time period after scheduling the first command. Prior to the first time period, a second command is identified according to a scheduling policy. A determination is made whether scheduling the second command on the command bus will cause a conflict in usage of the at least one data bus resource. In response to determining that scheduling the second command will cause the conflict in usage, a third lower-priority command is identified for which scheduling on the command bus will not cause the conflict in usage. The third command is scheduled on the command bus prior to scheduling the second command, even though it has lower priority than the second command.
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公开(公告)号：US12236090B2
公开(公告)日：2025-02-25
申请号：US18629743
申请日：2024-04-08
Applicant: Micron Technology, Inc.
Inventor： Donghua Zhou
IPC: G06F3/06
Abstract: Methods, systems, and apparatuses include receiving a current free space value and a historic delta value. A delta value is calculated using the current free space value, a target free space value, and the historic delta value. A delta region is determined using the delta value. A new host rate is calculated using the determined delta region, the calculated delta value, and the historic delta value. The new host rate is sent to a host device causing the host device to change a current host rate to the new host rate.
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公开(公告)号：US20250062230A1
公开(公告)日：2025-02-20
申请号：US18766403
申请日：2024-07-08
Applicant: Micron Technology, Inc.
Inventor： Darwin A. Clampitt
Abstract: A microelectronic device includes a first deck, a second deck, and a first conductive structure. The first deck has one or more memory cell strings and a stack of data lines operably connected to the one or more memory cell strings. Each of the one or more memory cell strings includes a first conductive contact. The second deck is vertically adjacent to the first deck and includes stacked tiers of conductive material defining a first interconnect structure. The first interconnect structure is operably connected to a data line of the stack of data lines. The first conductive structure is electrically coupled to the first conductive contact of the first deck and to the first interconnect structure of the second deck. Methods of forming the microelectronic device are also disclosed, as are memory devices, electronic signal processor devices, and electronic systems comprising such microelectronic devices.
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公开(公告)号：US20250061936A1
公开(公告)日：2025-02-20
申请号：US18754884
申请日：2024-06-26
Applicant: Micron Technology, Inc.
Inventor： Fatma Arzum Simsek-Ege , Haitao Liu
IPC: G11C11/408 , G11C11/4091 , G11C11/4097 , H10B12/00
Abstract: A microelectronic device includes a first die and a second die vertically overlying and attached to the first die. The first die includes an array region and a peripheral region horizontally neighboring the array region. The array region includes memory cells respectively including a first transistor structure, a second transistor structure horizontally neighboring the first transistor structure, and a storage device vertically underlying and coupled to the first transistor structure and the second transistor structure. The peripheral region includes sub word line driver circuitry. The second die includes sense amplifier regions and a CMOS region horizontally neighboring some of the sense amplifier regions. The sense amplifier regions are within a horizontal area of the array region of the first die and include sense amplifier circuitry. The CMOS region horizontally neighbors some of the sense amplifier regions and includes CMOS circuitry. Related memory devices and electronic systems are also described.
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公开(公告)号：US20250061070A1
公开(公告)日：2025-02-20
申请号：US18790391
申请日：2024-07-31
Applicant: Micron Technology, Inc.
Inventor： Sujeet Ayyapureddi
IPC: G06F13/16
Abstract: A memory device (e.g., a high-bandwidth (HBM) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. The memory die can include first memory banks associated with a first channel (e.g., having a first command address (CA) bus) and a first pseudo channel (e.g., having a first data (DQ) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second DQ bus). Operations can be performed at the first memory banks or the second memory banks in response to a command received through the first CA bus. The operations can cause data to be returned to circuitry that routes the data to an interface to the first DQ bus or an interface to the second DQ bus based on whether the data resulted from operations at the first memory banks or the second memory banks.
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公开(公告)号：US20250061065A1
公开(公告)日：2025-02-20
申请号：US18781989
申请日：2024-07-23
Applicant: Micron Technology, Inc.
Inventor： Melky Arputharaja Siluvainathan
Abstract: A first set of parameter values are programed to a first set of sequencer registers. A second set of parameter values are programmed to a second set of sequencer registers. In response to a detecting a triggering event, a hardware sequencer performs the following operations: transfer the first set of parameter values from the first set of sequencer registers to a first set of link training registers, transfer the second set of parameter values from the second set of sequencer registers to a second set of link training registers, and initiate one end of a communication link training with a host.
