公开(公告)号：US5621243A

公开(公告)日：1997-04-15

申请号：US363245

申请日：1994-12-23

申请人： Noboru Baba ,  Hisanori Okamura ,  Masahiko Sakamoto ,  Hirosi Akiyama ,  Ryuichi Saito ,  Yoshihiko Koike ,  Makoto Kitano ,  Sigeki Sekine ,  Hideya Kokubun ,  Nobuya Koike

发明人： Noboru Baba ,  Hisanori Okamura ,  Masahiko Sakamoto ,  Hirosi Akiyama ,  Ryuichi Saito ,  Yoshihiko Koike ,  Makoto Kitano ,  Sigeki Sekine ,  Hideya Kokubun ,  Nobuya Koike

IPC分类号： H01L23/373 ,  H01L25/07 ,  H01L23/34 ,  H05K7/20

CPC分类号： H01L23/3736 ,  H01L23/3735 ,  H01L25/072 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/19107 ,  H01L2924/3511

摘要： A high reliability electric power control semiconductor device with a prolonged product lifetime has been provided by successfully suppressing the metal support plate or the metal heat dissipation plate from warping due to the thermal stress during bonding so as to prevent the occurrences of cracks and gaps in the brazing fillers in the bonded layers between the metal heat dissipation plate or the metal support plate and the insulation plate in the semiconductor device comprising the semiconductor elements, metal heat dissipation plate, thermal stress buffer, insulation plate, and the metal support plate, wherein at least one of the metal heat dissipation plate and the metal support plate comprises a copper alloy of which a softening temperature at which a hot hardness of which becomes 1/2 of the hardness at the room temperature is 350.degree. C. or more. Further, in the semiconductor device fabricated by bonding the semiconductor elements via the thermal stress buffer, the heat dissipation plate and the insulation plate onto the metal support plate, the heat dissipation plate comprises a portion having a reduced thickness in the periphery thereof machined by counterboring or the like.

摘要翻译： 通过成功地抑制金属支撑板或金属散热板由于在接合期间的热应力引起的翘曲而提供具有延长的产品寿命的高可靠性电力控制半导体装置，以防止在 金属散热板或金属支撑板之间的接合层中的钎焊填料和包括半导体元件，金属散热板，热应力缓冲层，绝缘板和金属支撑板的半导体器件中的绝缘板，其中在 金属散热板和金属支撑板中的至少一个包括其热硬度变为+ E的软化温度，室温下的硬度的1/2 + EE的铜合金，为350℃ 。 或者更多。 此外，在将半导体元件经由热应力缓冲器，散热板和绝缘板接合到金属支撑板上而制造的半导体器件中，散热板包括通过对置加工而在其周边具有减小的厚度的部分 或类似物。

公开(公告)号：US08367479B2

公开(公告)日：2013-02-05

申请号：US12718200

申请日：2010-03-05

申请人： Hiroyuki Nakamura ,  Akira Muto ,  Nobuya Koike ,  Atsushi Nishikizawa ,  Yukihiro Sato ,  Katsuhiko Funatsu

发明人： Hiroyuki Nakamura ,  Akira Muto ,  Nobuya Koike ,  Atsushi Nishikizawa ,  Yukihiro Sato ,  Katsuhiko Funatsu

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/495 ,  H01L21/4828 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/838 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/05599

摘要： To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened.

公开(公告)号：US08298859B2

公开(公告)日：2012-10-30

申请号：US13035273

申请日：2011-02-25

申请人： Nobuya Koike ,  Tsukasa Matsushita ,  Hiroshi Sato ,  Keiichi Okawa ,  Atsushi Nishikizawa

发明人： Nobuya Koike ,  Tsukasa Matsushita ,  Hiroshi Sato ,  Keiichi Okawa ,  Atsushi Nishikizawa

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/49524 ,  H01L23/4952 ,  H01L24/03 ,  H01L24/05 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/84 ,  H01L24/91 ,  H01L29/7816 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/207

摘要： There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire.

摘要翻译： 需要提供一种能够降低将功率晶体管和控制集成电路集成到单个半导体芯片的半导体器件中的功率晶体管的导通电阻的技术。 另外需要提供能够减少半导体器件的芯片尺寸的技术。 半导体芯片包括形成功率晶体管的功率晶体管形成区域，形成逻辑电路的逻辑电路形成区域和形成模拟电路的模拟电路形成区域。 在功率晶体管形成区域中形成焊盘。 焊盘和引线通过横截面大于导线的夹子连接。 另一方面，焊盘通过导线连接。

公开(公告)号：US08232629B2

公开(公告)日：2012-07-31

申请号：US11841955

申请日：2007-08-20

申请人： Nobuya Koike ,  Atsushi Fujiki ,  Norio Kido ,  Yukihiro Sato ,  Hiroyuki Nakamura

发明人： Nobuya Koike ,  Atsushi Fujiki ,  Norio Kido ,  Yukihiro Sato ,  Hiroyuki Nakamura

IPC分类号： H01L23/495

CPC分类号： H01L21/565 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/04042 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device.A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.

摘要翻译： 通过改变半导体器件的结构，安装时的安装布线的布局变得有效。 第一芯片安装在第一芯片焊盘上，第二芯片也安装在第二芯片焊盘上。 第一管芯焊盘和第二管芯焊盘与密封体40的第一侧面和第二侧平行地进行分割结构。结果，用于从第一芯片输出的引脚和用于控制驱动电路的引脚 可以使其能够从反方向投影，并可以将安装时的布线布局设置为最小路线。

公开(公告)号：US20100308421A1

公开(公告)日：2010-12-09

申请号：US12767071

申请日：2010-04-26

申请人： Akira MUTO ,  Yuichi MACHIDA ,  Nobuya KOIKE ,  Atsushi FUJIKI ,  Masaki TAMURA

发明人： Akira MUTO ,  Yuichi MACHIDA ,  Nobuya KOIKE ,  Atsushi FUJIKI ,  Masaki TAMURA

IPC分类号： H01L27/088 ,  H01L23/52 ,  H01L23/28

CPC分类号： H01L25/074 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73253 ,  H01L2924/13091

摘要： The size of a semiconductor device is reduced. A semiconductor chip in which a power MOSFET is placed above a semiconductor chip in which another power MOSFET is formed and they are sealed with an encapsulation resin portion. The semiconductor chips are so arranged that the upper semiconductor chip does not overlap with the area positioned directly above a gate pad electrode of the lower semiconductor chip. The semiconductor chips are identical in size and the respective source pad electrodes and gate pad electrodes of the lower semiconductor chip and the upper semiconductor chip are identical in shape and arrangement. The lower semiconductor chip and the upper semiconductor chip are arranged with their respective centers displaced from each other.

摘要翻译： 半导体器件的尺寸减小。 一种半导体芯片，其中功率MOSFET被放置在其上形成另一功率MOSFET的半导体芯片之上，并且它们被密封树脂​​部分密封。 半导体芯片被布置成使得上半导体芯片不与位于下半导体芯片的栅极焊盘电极正下方的区域重叠。 半导体芯片的尺寸相同，并且下半导体芯片和上半导体芯片的各个源极焊盘电极和栅极焊盘电极的形状和布置相同。 下半导体芯片和上半导体芯片被布置成它们各自的中心彼此偏离。

公开(公告)号：US20090317948A1

公开(公告)日：2009-12-24

申请号：US12432075

申请日：2009-04-29

申请人： Hiroyuki NAKAMURA ,  Atsushi NISHIKIZAWA ,  Nobuya KOIKE

发明人： Hiroyuki NAKAMURA ,  Atsushi NISHIKIZAWA ,  Nobuya KOIKE

IPC分类号： H01L21/50 ,  H01L21/60

CPC分类号： H01L21/4835 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3426 ,  H05K2201/10795 ,  H05K2201/10909 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method is provided for manufacturing a QFN type semiconductor integrated circuit device using a multi-device lead frame having a tie bar for tying external end portions of plural leads, wherein sealing resin filled between an outer periphery of a mold cavity and the tie bar is removed by a laser and thereafter a surface treatment such as solder plating is performed.

摘要翻译： 提供一种使用具有用于捆扎多个引线的外端部的连接杆的多器件引线框架来制造QFN型半导体集成电路器件的方法，其中填充在模腔的外周和连接杆之间的密封树脂是 通过激光去除，然后进行诸如焊料镀覆的表面处理。

公开(公告)号：US20080054422A1

公开(公告)日：2008-03-06

申请号：US11841955

申请日：2007-08-20

申请人： Nobuya KOIKE ,  Atsushi FUJIKI ,  Norio KIDO ,  Yukihiro SATO ,  Hiroyuki NAKAMURA

发明人： Nobuya KOIKE ,  Atsushi FUJIKI ,  Norio KIDO ,  Yukihiro SATO ,  Hiroyuki NAKAMURA

IPC分类号： H01L23/495

CPC分类号： H01L21/565 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/04042 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device.A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.

摘要翻译： 通过改变半导体器件的结构，安装时的安装布线的布局变得有效。 第一芯片安装在第一芯片焊盘上，第二芯片也安装在第二芯片焊盘上。 第一管芯焊盘和第二管芯焊盘与密封体40的第一侧面和第二侧平行地进行分割结构。 结果，用于从第一芯片输出的引脚和用于控制驱动电路的引脚可使其能够从相反方向突出，并且可以将安装时的布线布局设置为最小路线 。

公开(公告)号：US20070040187A1

公开(公告)日：2007-02-22

申请号：US11503153

申请日：2006-08-14

申请人： Nobuya Koike ,  Tsukasa Matsushita ,  Hiroshi Sato ,  Keiichi Okawa ,  Atsushi Nishikizawa

发明人： Nobuya Koike ,  Tsukasa Matsushita ,  Hiroshi Sato ,  Keiichi Okawa ,  Atsushi Nishikizawa

IPC分类号： H01L31/111

CPC分类号： H01L23/49524 ,  H01L23/4952 ,  H01L24/03 ,  H01L24/05 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/84 ,  H01L24/91 ,  H01L29/7816 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/207

摘要： There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire 29.

摘要翻译： 需要提供一种能够降低将功率晶体管和控制集成电路集成到单个半导体芯片的半导体器件中的功率晶体管的导通电阻的技术。 另外需要提供能够减少半导体器件的芯片尺寸的技术。 半导体芯片包括形成功率晶体管的功率晶体管形成区域，形成逻辑电路的逻辑电路形成区域和形成模拟电路的模拟电路形成区域。 在功率晶体管形成区域中形成焊盘。 焊盘和引线通过横截面大于导线的夹子连接。 另一方面，焊盘通过导线29连接。

公开(公告)号：US06849933B2

公开(公告)日：2005-02-01

申请号：US10188805

申请日：2002-07-05

申请人： Nobuya Koike ,  Ichio Shimizu

发明人： Nobuya Koike ,  Ichio Shimizu

IPC分类号： H01L23/28 ,  H01L23/00 ,  H01L23/29 ,  H01L23/433 ,  H01L23/495 ,  H01L23/10 ,  H01L23/34

CPC分类号： H01L23/562 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A semiconductor device of a high heat radiation type having improved reliability is disclosed. The semiconductor device comprises a semiconductor chip with plural bonding pads formed thereon, plural inner leads, plural bonding wires for connecting the bonding pads and the inner leads with each other, a heat spreader having a chip supporting surface for supporting the semiconductor chip and also having a rear surface exposed to the exterior, a chip bonding material for bonding the semiconductor chip and the heat spreader with each other, a resin body which seals the semiconductor chip with a sealing resin, and plural outer leads projecting to the exterior from the resin body. A protruding portion protruding upward from the chip supporting surface is formed around the chip on the chip supporting surface of the heat spreader, thereby relieving a thermal stress imposed on an end portion of the chip bonding material and improving the reliability of a QFP as the semiconductor device.

摘要翻译： 公开了具有提高的可靠性的高放热型半导体器件。 半导体器件包括：多个接合焊盘形成的半导体芯片，多个内部引线，用于将接合焊盘和内部引线彼此连接的多个接合线，具有用于支撑半导体芯片的芯片支撑表面的散热器，并且还具有 暴露于外部的后表面，用于将半导体芯片和散热器彼此接合的芯片接合材料，用密封树脂密封半导体芯片的树脂体和从树脂体向外部突出的多个外部引线 。 在散热器的芯片支撑面上的芯片的周围形成有从芯片支撑面向上方突出的突出部，从而减轻了施加在芯片接合材料的端部上的热应力，提高了作为半导体的QFP的可靠性 设备。

公开(公告)号：US5808359A

公开(公告)日：1998-09-15

申请号：US547774

申请日：1995-10-25

申请人： Kuniharu Muto ,  Atsushi Nishikizawa ,  Jyunichi Tsuchiya ,  Toshiyuki Hata ,  Nobuya Koike ,  Ichio Shimizu

发明人： Kuniharu Muto ,  Atsushi Nishikizawa ,  Jyunichi Tsuchiya ,  Toshiyuki Hata ,  Nobuya Koike ,  Ichio Shimizu

IPC分类号： H01L23/28 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/60 ,  H01L23/02 ,  H01L23/29 ,  H01L23/433 ,  H01L23/495 ,  H01L23/36 ,  H01L23/34 ,  H01L23/50

CPC分类号： H01L23/4334 ,  H01L21/565 ,  H01L23/49541 ,  H01L2224/05554 ,  H01L2224/05639 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/181

摘要： A QFP adapted to lowering the heat resistance and increasing the number of pins includes a heat-radiating metal plate having bumpers formed at the four corners thereof as a unitary structure, a semiconductor chip mounted on the heat-radiating metal plate, leads provided on the heat-radiating metal plate and surrounding the peripheries of the semiconductor chip, bonding wires for connecting the leads to the semiconductor chip, and a sealing resin member for sealing part of the semiconductor chip, inner leads of the leads, bonding wires and part of the heat-radiating metal plate. The tips of the bumpers integrally formed with the heat-radiating metal plate are positioned outside the tips of the outer leads that are protruding from the sealing resin member. In the QFP producing method, the heat-radiating metal plate having the bumpers and the lead frame having the leads are secured outside the sealing resin member.

摘要翻译： 适于降低耐热性和增加引脚数量的QFP包括：散热金属板，其散热金属板在其四个角部处形成作为整体结构的缓冲器，安装在散热金属板上的半导体芯片， 散热金属板并且围绕半导体芯片的周边，用于将引线连接到半导体芯片的接合线，以及用于密封半导体芯片的一部分的密封树脂构件，引线的内部引线，接合线和部分 散热金属板。 与散热金属板一体形成的保险杠的前端位于从密封树脂构件突出的外引线的顶部的外侧。 在QFP制造方法中，具有保险杠的散热金属板和具有引线的引线框固定在密封树脂部件的外部。