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119 条记录 (耗时 0.032 秒)

    Wear leveling techniques for flash EEPROM systems
    11.
    发明授权
    Wear leveling techniques for flash EEPROM systems 失效

    公开(公告)号：US06594183B1

    公开(公告)日：2003-07-15

    申请号：US09108084

    申请日：1998-06-30

    申请人： Karl M. J. Lofgren ,  Robert D. Norman ,  Gregory B. Thelin ,  Anil Gupta

    发明人： Karl M. J. Lofgren ,  Robert D. Norman ,  Gregory B. Thelin ,  Anil Gupta

    IPC分类号： G11C1604

    CPC分类号： G11C16/3495 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211 ,  G11C8/12 ,  G11C16/349

    摘要： A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

    Method of controlling a memory device by way of a system bus
    12.
    发明授权
    Method of controlling a memory device by way of a system bus 有权
    通过系统总线控制存储器件的方法

    公开(公告)号：US06519691B2

    公开(公告)日：2003-02-11

    申请号：US09854343

    申请日：2001-05-11

    申请人： Vinod C. Lakhani ,  Robert D. Norman ,  Christophe J. Chevallier

    发明人： Vinod C. Lakhani ,  Robert D. Norman ,  Christophe J. Chevallier

    IPC分类号： G06F1200

    CPC分类号： G06F12/0661 ,  G06F2212/2022

    摘要： A non-volatile memory system having a memory controller, an array of memory cells and a memory operation manager. The operation manager carries out memory program, read and erase operation upon receipt of program, read and erase instruction from the controller, typically over a system bus. The address block circuitry is provided in the manager which is capable of performing an memory operation on a single address or on multiple addresses depending upon the state of the address block circuitry as determined by the controller. Multiple addresses can be generated based upon a single address provided by the controller so that sectors of the memory can be programmed or read thereby simplifying memory operations and reducing the overhead of the memory controller.

    摘要翻译： 具有存储器控制器，存储器单元阵列和存储器操作管理器的非易失性存储器系统。 操作管理器通常通过系统总线从控制器接收到程序，读取和擦除指令后执行存储器程序，读取和擦除操作。 在管理器中提供地址块电路，其能够根据由控制器确定的地址块电路的状态在单个地址或多个地址上执行存储器操作。 可以基于由控制器提供的单个地址来生成多个地址，使得可以编程或读取存储器的扇区，从而简化存储器操作并减少存储器控制器的开销。

    Multi-state flash memory defect management
    14.
    发明授权
    Multi-state flash memory defect management 失效
    多状态闪存缺陷管理

    公开(公告)号：US6034891A

    公开(公告)日：2000-03-07

    申请号：US980528

    申请日：1997-12-01

    申请人： Robert D. Norman

    发明人： Robert D. Norman

    IPC分类号： G11C16/06

    CPC分类号： G11C29/82 ,  G11C16/06

    摘要： A system is described which stores data intended for defective memory cells in a row of a memory array in an overhead location of the memory row. The data is stored in the overhead packet during a write operation, and is read from the overhead packet during a read operation. A defect location table for the row of the memory array is provided to identify when a defective memory cell is address;ed for either a read or write access operation. During a write operation, the correct data is stripped from incoming data for storing into the overhead packet. During a read operation, the correct data is inserted into an output data stream from the overhead packet. Data written to defective cells can be either a custom setting, a default setting, or the original data. Shift registers are described for holding good data during either a read or write operation. The number of shift registers used is determined by the number of states stored in a memory cell. The shift registers use a marker for alignment ofdata bits in a data stream.

    摘要翻译： 描述了一种系统，其将存储在存储器行的开销位置的存储器阵列的一行中的有缺陷的存储器单元的数据存储起来。 在写入操作期间将数据存储在开销数据包中，并且在读取操作期间从开销数据包读取数据。 提供用于存储器阵列行的缺陷位置表以识别缺陷存储器单元何时地址;用于读取或写入访问操作。 在写入操作期间，将正确的数据从传入数据中删除以存储到开销数据包中。 在读取操作期间，将正确的数据从开销数据包插入到输出数据流中。 写入缺陷单元格的数据可以是自定义设置，默认设置或原始数据。 描述移位寄存器用于在读取或写入操作期间保持良好的数据。 所使用的移位寄存器的数量由存储单元中存储的状态数确定。 移位寄存器使用数据流中数据位对齐的标记。

    System and method for writing data to memory cells so as to enable faster reads of the data using dual wordline drivers
    17.
    发明授权
    System and method for writing data to memory cells so as to enable faster reads of the data using dual wordline drivers 失效

    公开(公告)号：US5815458A

    公开(公告)日：1998-09-29

    申请号：US709555

    申请日：1996-09-06

    申请人： Christophe J. Chevallier ,  Vinod C. Lakhani ,  Robert D. Norman ,  Darrell D. Rinerson

    发明人： Christophe J. Chevallier ,  Vinod C. Lakhani ,  Robert D. Norman ,  Darrell D. Rinerson

    IPC分类号： G11C8/08 ,  G11C16/08 ,  G11C7/00

    CPC分类号： G11C16/08 ,  G11C8/08

    摘要： A memory system including an array of memory cells (e.g., flash memory cells) connected along wordlines and bitlines, two physically separated sets of wordline drivers (each for driving a different subset of the wordlines), and circuitry for writing data to selected cells connected along a selected wordline, where the cells are selected to be near the wordline driver for the wordline, to reduce the time needed for subsequent reads of the data, and a method implemented by such system. To write a sector of data (consisting of packets of the data) to cells connected along a wordline, the system preferably writes the first packet (or the first N bits of the first packet) to the cells which are physically nearest to the wordline driver which drives the wordline. In some embodiments, one set of wordline drivers (positioned along one side of the array) drives the even-numbered wordlines, another set of wordline drivers (positioned along the opposite side of the array) drives the odd-numbered wordlines, and the system exchanges the bitline addresses of the first packet and last packet (or the first N bytes of the first packet and the last N bytes of the last packet) of each sector to be written to cells along an even-numbered wordline (or inverts the bitline addresses for the entire sector), but the system does not modify the bitline address of any of data bit to be written to cells connected along an odd-numbered wordline. Preferably, the system is operable in either a first mode in which it modifies the addresses to which data is to be written to a cell array (to reduce the time needed to read the data after it has been written) or a second mode in which it does not modify the addresses to which the data is to be written to the array.

    Precision timing control programmable logic device
    20.
    发明授权
    Precision timing control programmable logic device 失效
    精密定时控制可编程逻辑器件

    公开(公告)号：US5239213A

    公开(公告)日：1993-08-24

    申请号：US897575

    申请日：1992-06-11

    申请人： Robert D. Norman ,  Sai-Keung Lee ,  Om Agrawal

    发明人： Robert D. Norman ,  Sai-Keung Lee ,  Om Agrawal

    IPC分类号： H03K3/037 ,  H03K5/15 ,  H03K19/177

    CPC分类号： H03K5/1504 ,  H03K19/17708 ,  H03K3/037

    摘要： A programmable logic device is disclosed having a delay line macrocell with programmably selectable taps feeding inputs to a programmable logic circuit. The delay line taps may feed the programmable logic circuit through logic circuit driving circuitry, which performs a certain amount of prepossessing on the tap signals before being provided to the programmable logic circuit. Outputs of the programmable logic circuit, which may be a programmable AND array followed by a fixed OR array, are provided to the edge-triggered inputs of dual set/reset flip flops. Other outputs of the programmable logic circuit are selectable as inputs to the delay line.

    摘要翻译： 公开了一种可编程逻辑器件，其具有延迟线宏单元，其具有可编程选择的抽头将输入馈送到可编程逻辑电路。 延迟线抽头可以通过逻辑电路驱动电路馈送可编程逻辑电路，逻辑电路驱动电路在提供给可编程逻辑电路之前对抽头信号执行一定量的预收。 可编程逻辑电路的输出可以被提供给双重设置/复位触发器的边沿触发输入，该可编程逻辑电路可以是可编程的AND数组，后面跟有一个固定的或数组。 可编程逻辑电路的其他输出可选择作为延迟线的输入。