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    JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE WITH P-TYPE SILICON GERMANIUM OR SILICON GERMANIUM CARBIDE GATE(S) AND METHOD OF FORMING THE STRUCTURE
    14.
    发明申请
    JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE WITH P-TYPE SILICON GERMANIUM OR SILICON GERMANIUM CARBIDE GATE(S) AND METHOD OF FORMING THE STRUCTURE 有权
    具有P型硅锗锗或碳化硅碳化硅栅的结型场效应晶体管结构及形成结构的方法

    公开(公告)号：US20120168820A1

    公开(公告)日：2012-07-05

    申请号：US12983489

    申请日：2011-01-03

    申请人： Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Xiaowei Tian

    发明人： Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Xiaowei Tian

    IPC分类号： H01L29/80 ,  H01L21/335

    CPC分类号： H01L29/66916 ,  H01L27/14679 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/808 ,  H01L29/8086

    摘要： Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.

    摘要翻译： 公开了具有一个或多个P型硅锗（SiGe）或硅碳化硅（SiGeC）栅极（即，SiGe或SiGeC基异质结JFET）的结型场效应晶体管（JFET）结构的实施例。 P型SiGe或SiGeC栅极允许较低的截止电压（即，较低的Voff），而不增加导通电阻（Ron）。 具体来说，P型栅极中的SiGe或SiGeC材料限制了P型掺杂物的扩散，从而确保了P型栅极与N型沟道区域结的关系更明确（即，与分级相反的突发性 ）。 通过明确定义该结，N型沟道区中的耗尽层延伸。 延伸耗尽层依次允许更快的夹断（即，需要更低的Voff）。 P型SiGe或SiGeC栅极可以结合到常规的横向JFET结构和/或垂直JFET结构中。 本文还公开了形成这种JFET结构的方法的实施例。

    Double gate depletion mode MOSFET
    16.
    发明授权
    Double gate depletion mode MOSFET 有权
    双栅耗尽型MOSFET

    公开(公告)号：US08168500B2

    公开(公告)日：2012-05-01

    申请号：US13013311

    申请日：2011-01-25

    申请人： John B. Campi ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

    发明人： John B. Campi ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/7838 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659

    摘要： A metal-oxide-semiconductor field effect transistor (MOSFET) has a body layer that follows the contour of exposed surfaces of a semiconductor substrate and contains a bottom surface of a shallow trench and adjoined sidewalls. A bottom electrode layer vertically abuts the body layer and provides an electrical bias to the body layer. A top electrode and source and drain regions are formed on the body layer. The thickness of the body layer is selected to allow full depletion of the body layer by the top electrode and a bottom electrode layer. The portion of the body layer underneath the shallow trench extends the length of a channel to enable a high voltage operation. Further, the MOSFET provides a double gate configuration and a tight control of the channel to enable a complete pinch-off of the channel and a low off-current in a compact volume.

    摘要翻译： 金属氧化物半导体场效应晶体管（MOSFET）具有跟随半导体衬底的暴露表面的轮廓的主体层，并且包含浅沟槽的底表面和相邻的侧壁。 底部电极层垂直邻接体层并向身体层提供电偏压。 顶部电极和源极和漏极区域形成在主体层上。 选择体层的厚度以允许顶层电极和底电极层完全耗尽体层。 浅沟槽下面的体层的部分延伸通道的长度以实现高电压操作。 此外，MOSFET提供双栅极配置和通道的严格控制，以实现通道的完全夹断和紧凑体积中的低截止电流。

    SELF-ALIGNED SCHOTTKY DIODE
    17.
    发明申请
    SELF-ALIGNED SCHOTTKY DIODE 有权
    自对准肖特基二极管

    公开(公告)号：US20110284961A1

    公开(公告)日：2011-11-24

    申请号：US13197414

    申请日：2011-08-03

    申请人： Alan B. Botula ,  Alvin J. Joseph ,  Alan F. Norris ,  Robert M. Rassel ,  Yun Shi

    发明人： Alan B. Botula ,  Alvin J. Joseph ,  Alan F. Norris ,  Robert M. Rassel ,  Yun Shi

    IPC分类号： H01L29/786 ,  G06F17/50 ,  G06F11/22

    CPC分类号： H01L29/7839 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/66659

    摘要： A Schottky barrier diode comprises a doped guard ring having a doping of a second conductivity type in a semiconductor-on-insulator (SOI) substrate. The Schottky barrier diode further comprises a first-conductivity-type-doped semiconductor region having a doping of a first conductivity type, which is the opposite of the second conductivity type, on one side of a dummy gate electrode and a Schottky barrier structure surrounded by the doped guard ring on the other side. A Schottky barrier region may be laterally surrounded by the dummy gate electrode and the doped guard ring. The doped guard ring includes an unmetallized portion of a gate-side second-conductivity-type-doped semiconductor region having a doping of a second conductivity type. A Schottky barrier region may be laterally surrounded by a doped guard ring including a gate-side doped semiconductor region and a STI-side doped semiconductor region. Design structures for the inventive Schottky barrier diode are also provided.

    摘要翻译： 肖特基势垒二极管包括在绝缘体上半导体（SOI）衬底中具有第二导电类型掺杂的掺杂保护环。 肖特基势垒二极管还包括在虚拟栅极电极的一侧上具有与第二导电类型相反的第一导电类型的掺杂的第一导电型掺杂半导体区域，以及被包围的肖特基势垒结构 另一侧的掺杂保护环。 肖特基势垒区域可以被伪栅电极和掺杂保护环横向包围。 掺杂保护环包括具有第二导电类型的掺杂的栅极侧第二导电型掺杂半导体区域的未金属化部分。 肖特基势垒区域可以由包括栅极掺杂半导体区域和STI侧掺杂半导体区域的掺杂保护环横向包围。 还提供了用于本发明的肖特基势垒二极管的设计结构。

    Asymmetric junction field effect transistor
    19.
    发明授权
    Asymmetric junction field effect transistor 有权
    非对称结场效应晶体管

    公开(公告)号：US07943445B2

    公开(公告)日：2011-05-17

    申请号：US12388586

    申请日：2009-02-19

    申请人： Frederick G. Anderson ,  David S. Collins ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

    发明人： Frederick G. Anderson ,  David S. Collins ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

    IPC分类号： H01L21/00 ,  H01L21/336

    CPC分类号： H01L29/1058 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66901 ,  H01L29/808

    摘要： A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.

    摘要翻译： 半导体衬底中的结型场效应晶体管（JFET）包括源极区，漏极区，沟道区，上部栅极区域和下部栅极区域。 下栅极区域电连接到上栅极区域。 上下栅极区域控制通过沟道区域的电流。 通过执行将源极区域的厚度延伸到大于漏极区域的厚度的深度的离子注入步骤，形成非对称JFET。 源极区域相对于漏极区域的深度的深度的扩展减小了少数电荷载流子穿过沟道区域的长度，减小了JFET的导通电阻，并增加了JFET的导通电流，由此 提高JFET的整体性能，而不会降低容许的Vds或显着增加Voff / Vpinch。

    Optimized device isolation
    20.
    发明授权
    Optimized device isolation 有权
    优化设备隔离

    公开(公告)号：US07868423B2

    公开(公告)日：2011-01-11

    申请号：US12269073

    申请日：2008-11-12

    申请人： John J. Benoit ,  David S. Collins ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Xuefeng Liu ,  Robert M. Rassel ,  Stephen A. St. Onge ,  James A. Slinkman

    发明人： John J. Benoit ,  David S. Collins ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Xuefeng Liu ,  Robert M. Rassel ,  Stephen A. St. Onge ,  James A. Slinkman

    IPC分类号： H01L21/02

    CPC分类号： H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0928

    摘要： A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions.

    摘要翻译： 用于半导体器件的结构包括具有三阱技术的隔离MOSFET（例如，NFET），其邻近隔离PFET，其本身与隔离的NFET相邻。 该结构包括其中在衬底内的任何n阱，p阱和p带区之下形成深n波段区的衬底。 一个p带区域形成在深n波段区域之上，隔离的MOSFET的隔离p阱下面，而另一个p波段区域形成在深n波段区域之上，并且在所有p-阱区下面， n阱，包括作为衬底内的隔离PFET和NFET器件的一部分的n阱。 隔离MOSFET的n阱连接到深n波段区域。 所得到的结构提供改进的器件隔离和降低从衬底传播到FET的噪声，同时保持三阱隔离区域的外部和内部的标准CMOS间隔布局间隔规则和电偏置特性。