公开(公告)号：US20100006952A1

公开(公告)日：2010-01-14

申请号：US12169118

申请日：2008-07-08

Applicant: Viorel Ontalus ,  Robert Robison

Inventor： Viorel Ontalus ,  Robert Robison

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: An FET and method of fabricating an FET. The method includes forming a gate dielectric layer on a top surface of a silicon region of a substrate and forming a gate electrode on a top surface of the gate dielectric layer; forming a source and a drain in the silicon region of and separated by a channel region under the gate electrode, the source having a source extension extending under the gate electrode and the drain having a drain extension extending under the gate electrode, the source, source extension, drain and drain extension doped a first type; and forming a source delta region contained entirely within the source and forming a drain delta region contained entirely within the drain, the delta source region and the delta drain region doped a second dopant type, the second dopant type opposite from the first dopant type.

Abstract translation: 一种FET及其制造方法。 该方法包括在衬底的硅区的顶表面上形成栅电介质层，并在栅电介质层的顶表面上形成栅电极; 在栅极电极下方的沟道区域中形成硅区域中的源极和漏极，源极和源极延伸延伸到栅电极下方，漏极延伸延伸到栅电极下方，源极源极 扩展，漏极和漏极延伸掺杂第一类型; 以及形成完全在所述源内包含的源极三角洲区域，并且形成完全在所述漏极内包含的漏极三角洲区域，所述δ源极区域和所述δ漏极区域掺杂第二掺杂剂类型，所述第二掺杂剂类型与所述第一掺杂剂类型相反。

公开(公告)号：US07855110B2

公开(公告)日：2010-12-21

申请号：US12169118

申请日：2008-07-08

Applicant: Viorel Ontalus ,  Robert Robison

Inventor： Viorel Ontalus ,  Robert Robison

IPC: H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: An FET and method of fabricating an FET. The method includes forming a gate dielectric layer on a top surface of a silicon region of a substrate and forming a gate electrode on a top surface of the gate dielectric layer; forming a source and a drain in the silicon region and separated by a channel region under the gate electrode, the source having a source extension extending under the gate electrode and the drain having a drain extension extending under the gate electrode, the source, source extension, drain and drain extension doped a first type; and forming a source delta region contained entirely within the source and forming a drain delta region contained entirely within the drain, the delta source region and the delta drain region doped a second dopant type, the second dopant type opposite from the first dopant type.

Abstract translation: 一种FET及其制造方法。 该方法包括在衬底的硅区的顶表面上形成栅电介质层，并在栅电介质层的顶表面上形成栅电极; 在硅区域中形成源极和漏极，并由栅电极下方的沟道区分隔开，源极具有在栅极下延伸的源极延伸，漏极具有在栅电极下延伸的漏极延伸，源极，源极延伸 ，漏极和漏极延伸掺杂第一类型; 以及形成完全在所述源内包含的源极三角洲区域，并且形成完全在所述漏极内包含的漏极三角洲区域，所述δ源极区域和所述δ漏极区域掺杂第二掺杂剂类型，所述第二掺杂剂类型与所述第一掺杂剂类型相反。

公开(公告)号：US20100041202A1

公开(公告)日：2010-02-18

申请号：US12191633

申请日：2008-08-14

Applicant: Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

Inventor： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

IPC: H01L21/02

CPC classification number: H01L23/5228 ,  H01L21/76816 ,  H01L23/5226 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines.

Abstract translation: 在一个实施例中，嵌入在第二介电层中的第二金属线覆盖在嵌入第一介电层中的第一金属线上。 覆盖第一金属线的第二电介质层的一部分使用光致抗蚀剂凹陷，第二金属线作为蚀刻掩模。 在凹槽内形成掺杂半导体衬垫，以在第一金属线和第二金属线之间提供电阻连接。 在另一个实施例中，第一金属线和第二金属线嵌入在电介质层中。 使用光致抗蚀剂和第一和第二金属线作为蚀刻掩模来凹入与第一和第二金属线横向邻接的电介质层的区域。 掺杂半导体衬垫形成在第一和第二金属线的侧壁上，提供第一和第二金属线之间的电阻连接。