公开(公告)号：US06194754B1

公开(公告)日：2001-02-27

申请号：US09263800

申请日：1999-03-05

Applicant: Sanjeev Aggarwal ,  Ramamoorthy Ramesh

Inventor： Sanjeev Aggarwal ,  Ramamoorthy Ramesh

IPC: H01L2976

CPC classification number: H01L21/7687 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/75

Abstract: A ferroelectric cell, particularly one integrated on a silicon substrate, comprising an amorphous barrier layer interposed between the ferroelectric stack and the silicon. Preferably, the ferroelectric stack includes conductive metal oxide electrodes sandwiching the ferroelectric layer. The metal oxide may act as a templating layer to crystallographically orient the ferroelectric layer. Alternatively, the electrodes and ferroelectric layer may be polycrystalline. The amorphous barrier layer may be composed of an intermetallic alloy, such as Ti3Al, a metal-metalloid, such as Pd—Si, a combination of early and later transition metals, such as Ti—Ni, and other related compound metal systems, such as (Ti, Zr)—Be, that form amorphous metals.

Abstract translation: 特别是集成在硅衬底上的铁电电池，包括介于铁电堆和硅之间的无定形阻挡层。 优选地，铁电体层包括夹着铁电体层的导电金属氧化物电极。 金属氧化物可以用作模板层以使铁电层晶体取向。 或者，电极和铁电层可以是多晶的。 无定形阻挡层可以由诸如Ti 3 Al的金属间合金，诸如Pd-Si的金属 - 准金属，诸如Ti-Ni的早期和稍后的过渡金属的组合以及其它相关的复合金属体系组成，例如 作为（Ti，Zr）-Be，形成无定形金属。

公开(公告)号：US20140220707A1

公开(公告)日：2014-08-07

申请号：US14219902

申请日：2014-03-19

Applicant: Sanjeev Aggarwal ,  Kerry Nagel ,  Jason Janesky

Inventor： Sanjeev Aggarwal ,  Kerry Nagel ,  Jason Janesky

IPC: H01L43/12

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer.

Abstract translation: 双隧道屏障磁性元件具有位于第一和第二隧道屏障之间的自由磁性层和位于第二隧道屏障上的电极。 两步蚀刻工艺允许在第一次蚀刻之后在电极的侧壁上形成封装材料，并且在进行第二蚀刻以去除自由层的一部分时防止第一隧道势垒的损坏。

公开(公告)号：US08236578B2

公开(公告)日：2012-08-07

申请号：US13358231

申请日：2012-01-25

Applicant: Phillip G. Mather ,  Sanjeev Aggarwal ,  Brian R. Butcher ,  Renu W. Dave ,  Frederick B. Mancoff ,  Nicholas D. Rizzo

Inventor： Phillip G. Mather ,  Sanjeev Aggarwal ,  Brian R. Butcher ,  Renu W. Dave ,  Frederick B. Mancoff ,  Nicholas D. Rizzo

IPC: H01L21/00

CPC classification number: H01L43/08 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/161 ,  H01L43/12

Abstract: A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.

公开(公告)号：US20120156806A1

公开(公告)日：2012-06-21

申请号：US13328874

申请日：2011-12-16

Applicant: Kerry Nagel ,  Kenneth Smith ,  Moazzem Hossain ,  Sanjeev Aggarwal

Inventor： Kerry Nagel ,  Kenneth Smith ,  Moazzem Hossain ,  Sanjeev Aggarwal

IPC: H01L21/20

CPC classification number: H01L43/12 ,  H01L21/28568 ,  H01L21/32133 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76877 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A conductive via for connecting between a digit line and one side of the magnetic device is positioned beneath, and aligned with, each magnetic device. Other contacts may satisfy the same design rules, using the same process step. An electrode formed on the conductive via is polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to at least a 45 nanometer node, a cell packing factor approaching 6F2, and a uniform thickness of material between the bit lines and the underlying memory elements.

Abstract translation: 用于连接磁性装置的数字线和一侧之间的导电通孔位于每个磁性装置的下方并对齐。 其他联系人可以使用相同的流程步骤来满足相同的设计规则。 抛光形成在导电通孔上的电极，以消除起始于导电通孔的步骤功能或接缝，从而向上传播通过各种沉积层。 该集成方法允许将MRAM器件改进至至少45纳米节点，接近6F2的电池封装因子以及位线和底层存储器元件之间材料的均匀厚度。

公开(公告)号：US07514734B2

公开(公告)日：2009-04-07

申请号：US11220292

申请日：2005-09-06

Applicant: Sanjeev Aggarwal ,  Kelly J. Taylor ,  Theodore S. Moise

Inventor： Sanjeev Aggarwal ,  Kelly J. Taylor ,  Theodore S. Moise

IPC: H01L29/76

CPC classification number: H01L27/11502 ,  H01L21/28568 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

Abstract: Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.

Abstract translation: 硬掩模和制造方法用于在半导体器件中制造铁电电容器，其中在上部电容器电极材料上方形成包括氧化铝或氧化钽锶的硬掩模，并蚀刻电容器电极和铁电层以限定铁电电容器叠层。

公开(公告)号：US20080290515A1

公开(公告)日：2008-11-27

申请号：US11753926

申请日：2007-05-25

Applicant: Valli Arunachalam ,  Satyavolu Srinivas Papa Rao ,  Sanjeev Aggarwal ,  Stephen Grunow

Inventor： Valli Arunachalam ,  Satyavolu Srinivas Papa Rao ,  Sanjeev Aggarwal ,  Stephen Grunow

IPC: H01L23/522 ,  H01L21/31 ,  H01L21/4763

CPC classification number: H01L23/53238 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of fabricating a diffusion barrier can include providing a dielectric layer, forming a first silicon enriched layer over the dielectric layer by exposing the dielectric layer to a silicon-containing ambient, and forming a barrier layer over the first silicon enriched layer.

Abstract translation: 根据本发明，存在扩散阻挡层，集成电路和半导体器件及其制造方法。 制造扩散阻挡层的方法可以包括提供电介质层，通过将电介质层暴露于含硅环境，在介电层上形成第一富硅层，并在第一富硅层上形成阻挡层。

公开(公告)号：US20060014378A1

公开(公告)日：2006-01-19

申请号：US10890663

申请日：2004-07-14

Applicant: Sanjeev Aggarwal ,  Kelly Taylor ,  Asad Haider ,  Alfred Griffin

Inventor： Sanjeev Aggarwal ,  Kelly Taylor ,  Asad Haider ,  Alfred Griffin

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76865 ,  H01L21/76873

Abstract: A method is disclosed to form a seed layer for an integrated circuit. The method may include depositing a metal seed layer (106) over a barrier layer (104) such that the metal seed layer (106) has a greater thickness along a top surface portion (114) of at least one recessed feature (102) formed in the substrate that is substantially coplanar with the substrate than a sidewall surface portion (112) of the at least one recessed feature (102). A portion of the metal seed layer (106) is etched from the top surface portion (114) of the at least one recessed feature (102) to improve coverage of the metal seed layer (106) along the sidewall surface portion (112) of the at least one recessed feature (102) and to mitigate overhang of the metal seed layer.

Abstract translation: 公开了形成用于集成电路的种子层的方法。 该方法可以包括在阻挡层（104）上沉积金属种子层（106），使得金属籽晶层（106）沿着形成的至少一个凹形特征（102）的顶表面部分（114）具有更大的厚度 在与所述至少一个凹陷特征（102）的侧壁表面部分（112）基本共面的基底中。 从所述至少一个凹陷特征（102）的顶表面部分（114）蚀刻所述金属种子层（106）的一部分，以改善所述金属种子层（106）沿着所述侧壁表面部分（112）的覆盖范围 所述至少一个凹陷特征（102）并且减轻所述金属种子层的突出部分。

公开(公告)号：US06984857B2

公开(公告)日：2006-01-10

申请号：US10620516

申请日：2003-07-16

Applicant: K. R. Udayakumar ,  Martin G. Albrecht ,  Theodore S. Moise, IV ,  Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Jeff L. Large

Inventor： K. R. Udayakumar ,  Martin G. Albrecht ,  Theodore S. Moise, IV ,  Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Jeff L. Large

IPC: H01L29/76

CPC classification number: H01L28/57 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of the ferroelectric material during back-end manufacturing processes employing hydrogen. The hydrogen barrier comprises silicon rich silicon oxide or amorphous silicon, which can be used in combination with an aluminum oxide layer to inhibit diffusion of process-related hydrogen into the ferroelectric capacitor layer.

Abstract translation: 提出了半导体器件和制造方法，其中在铁电电容器上方设置氢气阻挡层，以防止在使用氢的后端制造工艺期间铁电材料的劣化。 氢势垒包括富硅氧化物或非晶硅，其可以与氧化铝层组合使用以抑制工艺相关氢扩散到铁电电容器层中。

公开(公告)号：US06876021B2

公开(公告)日：2005-04-05

申请号：US10303560

申请日：2002-11-25

Applicant: J. Scott Martin ,  Scott R. Summerfelt ,  Theodore S. Moise ,  Kelly J. Taylor ,  Luigi Colombo ,  Sanjeev Aggarwal ,  Sirisha Kuchimanchi ,  K. R. Udayakumar ,  Lindsey Hall

Inventor： J. Scott Martin ,  Scott R. Summerfelt ,  Theodore S. Moise ,  Kelly J. Taylor ,  Luigi Colombo ,  Sanjeev Aggarwal ,  Sirisha Kuchimanchi ,  K. R. Udayakumar ,  Lindsey Hall

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L31/119

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55

Abstract: The present invention forms sidewall diffusion barrier layer(s) that mitigate hydrogen contamination of ferroelectric capacitors. Sidewall diffusion barrier layer(s) of the present invention are formed via a physical vapor deposition process at a low temperature. By so doing, the sidewall diffusion barrier layer(s) are substantially amorphous and provide superior protection against hydrogen diffusion than conventional and/or crystalline sidewall diffusion barrier layers.

Abstract translation: 本发明形成减轻铁电电容器的氢污染的侧壁扩散阻挡层。 本发明的侧壁扩散阻挡层通过物理气相沉积工艺在低温下形成。 通过这样做，侧壁扩散阻挡层基本上是无定形的，并提供优于常规和/或结晶侧壁扩散阻挡层的氢气扩散保护。

公开(公告)号：US06828161B2

公开(公告)日：2004-12-07

申请号：US10313068

申请日：2002-12-06

Applicant: Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Luigi Colombo ,  Theodore S. Moise, IV ,  J. Scott Martin

Inventor： Scott R. Summerfelt ,  Sanjeev Aggarwal ,  Luigi Colombo ,  Theodore S. Moise, IV ,  J. Scott Martin

IPC: H01L2100

CPC classification number: H01L27/11502 ,  H01L27/11507

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a multi-layer hard mask. The multi-layer hard mask comprises a hard masking layer overlying an etch stop layer. The etch stop layer is substantially more selective than the overlying masking layer with respect to an etch employed to remove the bottom electrode diffusion barrier layer. Therefore during an etch of the capacitor stack, an etch of the bottom electrode diffusion barrier layer results in a substantially complete removal of the hard masking layer. However, due to the substantial selectivity (e.g., 10:1 or more) of the etch stop layer with respect to the overlying masking layer, the etch stop layer completely protects the underlying top electrode, thereby preventing exposure thereof.

Abstract translation: 本发明涉及一种形成FeRAM集成电路的方法，其包括形成多层硬掩模。 多层硬掩模包括覆盖在蚀刻停止层上的硬掩模层。 相对于用于去除底部电极扩散阻挡层的蚀刻，蚀刻停止层比上覆掩模层更具选择性。 因此，在电容器堆叠的蚀刻期间，底部电极扩散阻挡层的蚀刻导致硬掩模层的基本上完全去除。 然而，由于蚀刻停止层相对于上覆掩模层的实质选择性（例如10:1或更多），蚀刻停止层完全保护下面的顶部电极，从而防止其暴露。