公开(公告)号：US5963501A

公开(公告)日：1999-10-05

申请号：US96447

申请日：1998-06-11

Applicant: Sung-geun Lee ,  Woo-seop Jeong

Inventor： Sung-geun Lee ,  Woo-seop Jeong

IPC: G11C11/407 ,  G06F1/04 ,  G11C7/22 ,  G11C11/409 ,  H03K3/02 ,  G11C8/00

CPC classification number: G11C7/22

Abstract: A clock signal generating circuit for use in a synchronous dynamic random access memory device. The clock signal generating circuit includes an input buffer for converting an externally supplied system clock signal having a first voltage level into a clock signal having a voltage level necessary for operating with the internal circuitry of the memory device. An enable path circuit generates a second transition of an internal clock signal which occurs substantially simultaneous the second transition of the system clock signal. The enable path circuit generates the first transition of the internal clock signal after the internal clock signal is maintained at the second state for a predetermined interval responsive to first and second disable signals. Finally, a disable path circuit receives the clock signal generated from the input buffer and supplies the first and second disable signals to the enable path circuit.

Abstract translation: 一种用于同步动态随机存取存储器件的时钟信号发生电路。 时钟信号发生电路包括用于将外部提供的具有第一电压电平的系统时钟信号转换为具有与存储器件的内部电路一起操作所需的电压电平的时钟信号的输入缓冲器。 使能路径电路产生基本上同时发生系统时钟信号的第二转换的内部时钟信号的第二转变。 在第一和第二禁止信号之后，使能路径电路在内部时钟信号被保持在第二状态一段预定间隔之后产生内部时钟信号的第一转变。 最后，禁用路径电路接收从输入缓冲器产生的时钟信号，并将第一和第二禁止信号提供给使能路径电路。