公开(公告)号：US5008721A

公开(公告)日：1991-04-16

申请号：US494042

申请日：1990-03-15

Applicant: Manzur Gill ,  Sung-Wei Lin ,  C. Rinn Cleavelin ,  David J. McElroy

Inventor： Manzur Gill ,  Sung-Wei Lin ,  C. Rinn Cleavelin ,  David J. McElroy

IPC: H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/11517 ,  H01L29/7883 ,  Y10S257/903

Abstract: An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.

Abstract translation: 使用与浮栅晶体管合并的增强型晶体管构造电可擦除的电可编程ROM或EEPROM，其中浮栅晶体管具有位于源极的相对侧上的小的自对准隧道窗口 通道和漏极，无接触电池布局，增强了制造的便利性和减小电池尺寸。 在该单元中，位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。 编程和擦除由源外部的隧道窗口区域（与通道间隔开）提供。 隧道窗口具有比浮动门的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。

公开(公告)号：US20080084773A1

公开(公告)日：2008-04-10

申请号：US11543338

申请日：2006-10-04

Applicant: Sudhir Kumar Madan ,  Hugh P. Mcadams ,  Sung-Wei Lin

Inventor： Sudhir Kumar Madan ,  Hugh P. Mcadams ,  Sung-Wei Lin

IPC: G11C11/22 ,  G11C7/00 ,  G11C7/02

CPC classification number: G11C11/22 ,  G11C2207/005 ,  G11C2207/2281 ,  G11C2207/229

Abstract: One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.

Abstract translation: 本发明的一个方面涉及一种用于访问存储器件的方法。 一个实施例涉及访问存储器件的方法。 在读操作期间的方法中，在本地IO线上提供一个数据值，而与本地IO线相关联的互补本地IO线被停用。 在写操作期间，本地IO线上提供另一个数据值，并在互补的本地IO线上提供补充数据值。 还公开了其它系统和方法。

公开(公告)号：US5646894A

公开(公告)日：1997-07-08

申请号：US560771

申请日：1995-11-21

Applicant: Sung-Wei Lin ,  Tim M. Coffman ,  Ronald J. Syzdek

Inventor： Sung-Wei Lin ,  Tim M. Coffman ,  Ronald J. Syzdek

IPC: G11C17/00 ,  G11C8/08 ,  G11C16/06 ,  G11C11/40

CPC classification number: G11C8/08

Abstract: The circuit of this invention improves significantly the programming speed of a Flash EPROM. The circuit includes a detector circuit (DC) using a pre-charge capacitor (C1), capacitor dividers [(C1/(C1+C2) and C3/(C2+C3)] and a voltage comparator (COMP) to signal a control logic circuit (CLC) when the programming voltage is within supply voltage (V.sub.cc) of its final value. At that point the control logic circuit (CLC) boosts the voltage on one terminal of a boost capacitor (BC) by the value of the supply voltage (V.sub.cc). The other terminal (XDD) of the boost capacitor (BC) furnishes the boosted programming voltage for the Flash EPROM.

Abstract translation: 本发明的电路显着地改善了闪存EPROM的编程速度。 该电路包括使用预充电电容器（C1），电容分压器[（C1 /（C1 + C2）和C3 /（C2 + C3）]）和电压比较器（COMP）的检测器电路（DC） 逻辑电路（CLC），当编程电压在其最终值的电源电压（Vcc）之内时，控制逻辑电路（CLC）将升压电容器（BC）的一个端子上的电压提高到电源的电压 电压（Vcc），升压电容（BC）的另一端（XDD）为闪存EPROM提供升压编程电压。

公开(公告)号：US5424992A

公开(公告)日：1995-06-13

申请号：US112484

申请日：1993-08-25

Applicant: Tim M. Coffman ,  Sung-Wei Lin ,  Dennis R. Robinson ,  Phat C. Truong ,  T. Damodar Reddy

Inventor： Tim M. Coffman ,  Sung-Wei Lin ,  Dennis R. Robinson ,  Phat C. Truong ,  T. Damodar Reddy

IPC: G11C16/16 ,  G11C13/00

CPC classification number: G11C16/16

Abstract: An array source signal discharge controller device (10) includes a pulse converter circuit (12) that receives an erase pulse signal (ERPULSE). The pulse converter circuit (12) converts the erase pulse signal (ERPULSE) into a pulse control signal (ERPCL) that is subsequently translated into a higher voltage level bias signal (ECL.sub.--). The higher voltage level bias signal (ECL.sub.--) drives array source signal generator circuits (16) that produce array source signals (AS) to erase particular array subsections of memory as determined by a selection circuit (17). The array source signal generator circuits (16) also generate array source command signals (ASCOM.sub.--) to indicate a discharging status of all array source signals (AS). An erase completion detector circuit (18) monitors the array source command signals (ASCOM.sub.--) and generates an array source detect signal (ASDET) to indicate completion of array source signal (AS) discharging. The pulse converter circuit (12) receives the array source detect signal (ASDET) and generates an erase completion signal (ERCTR) and a pulldown control signal ERCTR.sub.-- to control final discharge of the array source signals (AS) and indicate that normal memory access may resume. The pulse converter circuit (12) also generates a pulldown signal (ERD.sub.--) that controls discharge of the array source signals (AS) by preventing current surges from appearing on the array source signals (AS) during discharge.

Abstract translation: 阵列源信号放电控制器装置（10）包括接收擦除脉冲信号（ERPULSE）的脉冲转换器电路（12）。 脉冲转换器电路（12）将擦除脉冲信号（ERPULSE）转换成脉冲控制信号（ERPCL），随后将其转换为更高的电压电平偏置信号（ECL-）。 较高电压电平偏置信号（ECL-）驱动产生阵列源信号（AS）的阵列源信号发生器电路（16），以擦除由选择电路（17）确定的存储器的特定阵列子部分。 阵列源信号发生器电路（16）还产生阵列源指令信号（ASCOM-），以指示所有阵列源信号（AS）的放电状态。 擦除完成检测电路（18）监视阵列源指令信号（ASCOM-）并产生阵列源检测信号（ASDET），以指示阵列源信号（AS）放电完成。 脉冲转换器电路（12）接收阵列源检测信号（ASDET）并产生擦除完成信号（ERCTR）和下拉控制信号ERCTR-以控制阵列源信号（AS）的最终放电，并指示正常存储器存取 可能会恢复。 脉冲转换器电路（12）还通过在放电期间防止在阵列源信号（AS）上出现电流浪涌来产生控制阵列源信号（AS）的放电的下拉信号（ERD-）。

公开(公告)号：US5396115A

公开(公告)日：1995-03-07

申请号：US149245

申请日：1993-10-26

Applicant: Tim M. Coffman ,  Phat C. Truong ,  Sung-Wei Lin ,  T. Damodar Reddy ,  Dennis R. Robinson

Inventor： Tim M. Coffman ,  Phat C. Truong ,  Sung-Wei Lin ,  T. Damodar Reddy ,  Dennis R. Robinson

IPC: H03K5/04 ,  H03K17/22

CPC classification number: G06F1/28 ,  G06F1/24 ,  H03K17/223 ,  H03K5/04

Abstract: The power-on reset circuit of this invention includes a current-sensing circuit, a pulse-stretching circuit, and a voltage-reference circuit. The voltage-reference circuit consists, for example, of one N-Channel and one P-Channel MOS transistor. The circuit of this invention uses a static voltage reference comprised of CMOS transistors to detect the power-up condition. The circuit of this invention improves detection of a transient power-supply voltage Vcc loss and detects that power-supply voltage transient on both rising and falling edges.

Abstract translation: 本发明的上电复位电路包括电流检测电路，脉冲拉伸电路和电压参考电路。 电压基准电路例如由一个N沟道和一个P沟道MOS晶体管组成。 本发明的电路使用由CMOS晶体管组成的静态参考电压来检测上电状态。 本发明的电路改进了瞬态电源电压Vcc损耗的检测，并检测上升沿和下降沿的电源电压瞬变。

公开(公告)号：US5392248A

公开(公告)日：1995-02-21

申请号：US149242

申请日：1993-10-26

Applicant: Phat C. Truong ,  Tim M. Coffman ,  Sung-Wei Lin ,  T. Damodar Reddy ,  Dennis R. Robinson

Inventor： Phat C. Truong ,  Tim M. Coffman ,  Sung-Wei Lin ,  T. Damodar Reddy ,  Dennis R. Robinson

IPC: G11C29/02 ,  G11C29/18 ,  G11C29/50 ,  G11C7/00

CPC classification number: G11C29/025 ,  G11C29/02 ,  G11C29/18 ,  G11C29/50 ,  G11C16/04 ,  G11C2029/5006

Abstract: The column-line short detection circuit of this invention includes a special test circuit that turns off wordlines (15), a N-channel transistor (23) for each column line (18), a decoder (19a) that uses only the least significant column address (20d) for input to the test circuit, and a sensor (SA) to detect current between shorted column lines (18). Because the column-line short detection circuit of this invention uses only the least significant address as input for column decoder (19a), it requires a very small number of transistors.

Abstract translation: 本发明的列线短路检测电路包括一个特殊的测试电路，它关闭字线（15），用于每列列线（18）的N沟道晶体管（23），仅使用最不重要的解码器（19a） 用于输入到测试电路的列地址（20d）和用于检测短路列线（18）之间的电流的传感器（SA）。 因为本发明的列线短路检测电路仅使用最低有效地址作为列解码器（19a）的输入，所以它需要非常少数量的晶体管。

公开(公告)号：US5187683A

公开(公告)日：1993-02-16

申请号：US576307

申请日：1990-08-31

Applicant: Manzur Gill ,  Sung-Wei Lin ,  Sebastiano D'Arrigo

Inventor： Manzur Gill ,  Sung-Wei Lin ,  Sebastiano D'Arrigo

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/08 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115

CPC classification number: G11C16/08 ,  G11C16/10

Abstract: A method is described for programming a semiconductor array of EEPROM cells. A selected cell is connected, by definition, to a selected source-column line, a selected drain-column line and a selected wordline. Each deselected memory cell in the array is connected to a deselected source-column line, a deselected drain-column line and/or a deselected wordline. The method includes preselecting first, second, third, fourth and fifth programming voltages such that the second programming voltage is more positive than the first programming voltage and such that the third, fourth and fifth programming voltages are intermediate between the first and second programming voltages. The first programming voltage is applied at least to a selected column line and to each of the same-type deselected column lines. The third programming voltage is applied to the selected wordline and the fourth programming voltage is applied to each deselected wordline. After a pre-charge time interval, the fifth programming voltage is applied to each same-type deselected column line and, after an optional additional pre-charge time interval, the second programming voltage is applied to the selected wordline. After a program time interval, the third programming voltage is applied to the selected wordline and, after an optional discharge time interval, the first programming voltage is applied to each same-type deselected column line. Each deselected wordline is maintained at the fourth programming voltage for an additional discharge time interval. The third, fourth and fifth programming voltages may have the same value.

Abstract translation: 描述了一种用于编程EEPROM单元的半导体阵列的方法。 根据定义，所选择的单元格连接到所选择的源列行，所选的排列列线和所选择的字线。 阵列中的每个取消选择的存储单元连接到未选择的源 - 列线，取消选择的漏 - 列线和/或未选择的字线。 该方法包括预选第一，第二，第三，第四和第五编程电压，使得第二编程电压比第一编程电压更正，并且使得第三，第四和第五编程电压在第一和第二编程电压之间。 至少将第一编程电压施加到所选择的列线和每个相同类型的未选择的列线。 将第三编程电压施加到所选择的字线，并且将第四编程电压施加到每个取消选择的字线。 在预充电时间间隔之后，将第五编程电压施加到每个相同类型的未选择的列线，并且在可选的附加预充电时间间隔之后，将第二编程电压施加到所选择的字线。 在编程时间间隔之后，将第三编程电压施加到所选择的字线，并且在可选的放电时间间隔之后，将第一编程电压施加到每个相同类型的未选择的列线。 每个取消选择的字线保持在第四个编程电压下一个额外的放电时间间隔。 第三，第四和第五编程电压可以具有相同的值。

公开(公告)号：US5168335A

公开(公告)日：1992-12-01

申请号：US741975

申请日：1991-08-06

Applicant: Iano D'Arrigo ,  Manzur Gill ,  Sung-Wei Lin

Inventor： Iano D'Arrigo ,  Manzur Gill ,  Sung-Wei Lin

IPC: H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/11517 ,  H01L29/7883

Abstract: A pair of electrically erasable, electrically programmable memory cells are formed at a face of a semiconductor layer (10) and include respective source regions (30a, 30b), a shared drain region (28) and respective channel regions (38a, 38b). Each cell has a floating gate conductor (46a, 46b) that controls the conductance of a respective subchannel region (74a, 74b) and may be programmed through Fowler-Nordheim electron tunneling through a respective tunnel oxide window (40a, 40b) from a respective source region (30a, 30b). A field plate conductor (40a) controls the conductance of respective subchannel regions (70a, 70b) within each channel region (38a, 38b). A word line or control gate conductor (62) is insulatively disposed adjacent respective third, remaining channel subregions (53a, 53b) and further is disposed insulatively adjacent the floating gates (46a, 46b) to program or erase them.

Abstract translation: 在半导体层（10）的表面上形成一对电可擦除的电可编程存储单元，并且包括各自的源极区（30a，30b），共用漏极区（28）和各个沟道区（38a，38b）。 每个单元具有控制相应子通道区域（74a，74b）的电导的浮栅导体（46a，46b），并且可以通过Fowler-Nordheim电子隧穿通过相应的隧道氧化物窗（40a，40b）从相应的 源区域（30a，30b）。 场板导体（40a）控制每个通道区域（38a，38b）内各个子通道区域（70a，70b）的电导。 字线或控制栅极导体（62）被绝对地设置在相邻的第三剩余通道子区域（53a，53b）附近，并且还与浮动栅极（46a，46b）绝缘地设置以编程或擦除它们。

公开(公告)号：US5156991A

公开(公告)日：1992-10-20

申请号：US648087

申请日：1991-01-31

Applicant: Manzur Gill ,  Sebastiano D'Arrigo ,  Sung-Wei Lin

Inventor： Manzur Gill ,  Sebastiano D'Arrigo ,  Sung-Wei Lin

IPC: H01L27/115 ,  H01L29/788

CPC classification number: H01L27/115 ,  H01L29/7883 ,  Y10S438/981

Abstract: An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window are near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between wordlines is also by thick thermal oxide in a preferred embodiment, further improving the coupling ratio. Bitline and wordline spacing may be selected for optimum pitch or aspect ratio. Bitline to substrate capacitance is minimized.

Abstract translation: 使用与浮栅晶体管合并的增强晶体管构造电可擦除可编程ROM单元或EEPROM单元，其中浮栅晶体管具有小的隧道窗，无接触电池布局，增强了 易于制造和减小电池尺寸。 位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。 隧道窗口提供的编程和擦除靠近或高于源的通道侧。 窗口具有比浮动栅极的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。 通过使用专用的漏极或接地线，而不是虚拟接地布局，并且通过使用厚氧化物在位线之间隔离，浮动栅极可以延伸到相邻的位线和隔离区域，从而产生良好的耦合比。 在优选实施例中，字线之间的隔离也是厚氧化物，进一步提高了耦合比。 可以选择位线和字线间距来获得最佳间距或宽高比。 位线到基板电容最小化。

公开(公告)号：US20090034338A1

公开(公告)日：2009-02-05

申请号：US12102125

申请日：2008-04-14

Applicant: Sung-Wei Lin ,  Stephen Keith Heinrich-Barna

Inventor： Sung-Wei Lin ,  Stephen Keith Heinrich-Barna

IPC: G11C16/06 ,  G11C7/00

CPC classification number: G11C16/28 ,  G11C16/30

Abstract: One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to generate a bit-line current on the bit-line node in response to a bias voltage during a read operation. The system further comprises a sense amplifier configured to maintain a substantially constant voltage magnitude of the bit-line node during a pre-charge phase and a sense phase of the read operation based on regulating current flow to and from the bit-line node, and to determine a memory value of the flash memory transistor during the read operation based on a magnitude of the bit-line current on the bit-line node.

Abstract translation: 本发明的一个实施例包括存储器系统。 该系统包括耦合到位线节点的存储器单元。 存储器单元可被配置为在读取操作期间响应于偏置电压而在位线节点上产生位线电流。 该系统还包括读出放大器，其被配置为在预充电阶段期间保持位线节点的基本上恒定的电压幅值，并且基于调节到位线节点和从位线节点的电流流动来读取操作的感测相位，以及 以在读取操作期间基于位线节点上的位线电流的大小来确定闪存晶体管的存储器值。