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11.发明申请公开(公告)号：US20090011728A1
公开(公告)日：2009-01-08
申请号：US12216092
申请日：2008-06-30
CPC分类号： H03F1/0227 , H03F1/0205 , H03F1/32 , H03F3/24 , H03F2200/102 , H03F2200/99
摘要： A DCDC converter includes a signal splitting unit that splits an input signal into N signal components; N DCDC converter elements that process individually the N split signals; and an adder that adds outputs from the plural DCDC converter elements to generate output signals. Each of the DCDC converter elements has an operation band narrower than an applicable frequency band of the input signal, and selects a design parameter that allows a conversion efficiency of the DCDC converter elements to be optimized for any band of the applicable frequency bands. For example, the parameter of a PMOS transistor and a NMOS transistor, which configure an inverter is designed to optimize the efficiency at any of frequency bands. The frequency band of the input signal is split, and each of the split outputs is input to a DCDC converter element that has a corresponding frequency and high efficiency characteristic.
摘要翻译： DCDC转换器包括将输入信号分解为N个信号分量的信号分离单元; N个DCDC转换器元件，分别处理N个分离信号; 以及加法器，其添加来自多个DCDC转换器元件的输出以产生输出信号。 每个DCDC转换器元件具有比输入信号的适用频带窄的操作频带，并且选择允许DCDC转换器元件的转换效率针对适用频带的任何频带进行优化的设计参数。 例如，配置反相器的PMOS晶体管和NMOS晶体管的参数被设计为优化任何频带处的效率。 输入信号的频带被分离，并且每个分离输出被输入到具有对应的频率和高效率特性的DCDC转换器元件。
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公开(公告)号：US07444123B2
公开(公告)日：2008-10-28
申请号：US11335510
申请日：2006-01-20
申请人： Taizo Yamawaki , Yoshiaki Harasawa
发明人： Taizo Yamawaki , Yoshiaki Harasawa
CPC分类号： H04B1/04 , H04B1/406 , H04B2001/0416
摘要： With a dual mode transmitter capable of handling two modulation methods for nonconstant amplitude modulation and constant amplitude modulation, respectively, speed-up of transition between modes is implemented. In a mode handling the constant amplitude modulation, first capacitors included in a low-pass filter constituting an AM loop, and a second capacitor included in an integrator are kept recharged from a first constant-voltage power supply and a second constant-voltage power supply by use of a first switch and a second switch, respectively. By doing so, a value of voltage to be recharged at the time of a mode changeover is decreased, and further, a first variable-gain amplifier starts control of a gain while avoiding a region where the output voltage of the first variable-gain amplifier has slow response against an input voltage.
摘要翻译： 利用双模式发射机能够分别处理非恒定幅度调制和恒定幅度调制的两种调制方式，实现了模式间转换的加速。 在处理恒定幅度调制的模式中，包括在构成AM环路的低通滤波器中的第一电容器和积分器中包括的第二电容器从第一恒压电源和第二恒压电源保持再充电 分别使用第一开关和第二开关。 通过这样做，减少在模式切换时要再充电的电压值，此外，第一可变增益放大器开始增益控制，同时避免第一可变增益放大器的输出电压 对输入电压响应缓慢。
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公开(公告)号：US07424276B2
公开(公告)日：2008-09-09
申请号：US10509753
申请日：2003-02-18
IPC分类号： H04B1/04
CPC分类号： H03G3/3042 , H03F1/34 , H03F3/24 , H04B1/0475 , H04B2001/0433 , H04L27/361
摘要： In a transmitter of polar-loop architecture having a phase control loop and an amplitude control loop, as loop filters for controlling a loop band of the amplitude control loop, a first filter with lag-lead characteristics (secondary or more filter including a capacitor and a resistor) and a second filter of a perfect integrator type (filter including only a capacitor) are employed, and current-output type circuits are connected to respective front stages of the first and second filters.
摘要翻译： 在具有相位控制环路和幅度控制环路的极性环路架构的发射机中，作为用于控制振幅控制环路的环路频带的环路滤波器，具有滞后引线特性的第一滤波器（包括电容器和 电阻器）和完美积分器型（仅包括电容器的滤波器）的第二滤波器，并且电流输出型电路连接到第一和第二滤波器的各个前级。
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14.发明授权公开(公告)号：US07333779B2
公开(公告)日：2008-02-19
申请号：US11121018
申请日：2005-05-04
CPC分类号： H03L7/10 , H03D13/007 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/12 , H04B1/406
摘要： In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.
摘要翻译： 在PLL电路中，将LPF的数量减少到一个，以减少安装面积和引脚数量，并简化设计。 在一个实施例中，PLL电路包括可变增益相位比较器，混频器，LPF，VCO，耦合器以及控制VCO的开/关操作的控制电路。 可变增益相位比较器能够改变相位差增益。 VCO的操作的开/关由控制电路控制，使得VCO中的一个被关断。 相位差转换增益根据VCO的灵敏度而变化，因此PLL电路所需的LPF的数量可以减少到一个。
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公开(公告)号：US20060135093A1
公开(公告)日：2006-06-22
申请号：US11304914
申请日：2005-12-16
申请人： Masahiro Ito , Taizo Yamawaki , Yoshiaki Harasawa
发明人： Masahiro Ito , Taizo Yamawaki , Yoshiaki Harasawa
IPC分类号： H01Q11/12
CPC分类号： H04B1/0475 , H03F1/0205 , H03F1/0261 , H03F2200/294
摘要： A transmitter employing variable gain amplifiers and operating with both constant and nonconstant envelope modulation systems is contrived to suppress variation in the transmitting power when constant envelope modulation is performed. The transmitter comprises a PM loop, an AM loop, and a variable gain amplifier which is shared by the PM loop and the AM loop and combines phase information that the PM loop outputs and envelope information that the AM loop outputs by gain control. The variable gain amplifier comprises a variable gain amplifier body having a supply voltage terminal and a bias current detection terminal for extracting a bias current corresponding to a gain, wherein the gain changes with a change in the potential of the supply voltage terminal, and a bias control block connected to the supply voltage terminal and the bias current detection terminal. Thereby, a bias control loop is formed to control the bias current so that the gain in the case of constant envelope modulation becomes a predetermined value.
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公开(公告)号：US20050220217A1
公开(公告)日：2005-10-06
申请号：US11017076
申请日：2004-12-21
申请人： Taizo Yamawaki , Masahiro Ito , Masumi Kasahara , Hiroaki Matsui
发明人： Taizo Yamawaki , Masahiro Ito , Masumi Kasahara , Hiroaki Matsui
CPC分类号： H04L27/0008 , H03F1/02 , H03F3/24 , H04B2001/045
摘要： A transmitter that can reduce noise without using an SAW filter whose IC integration is hard, and copes with two modulation formats of constant envelope modulation and non-constant envelope modulation, and a downsized and low-cost wireless communication apparatus that uses the transmitter are provided. The transmitter includes a quadrature modulator that modulates an input signal by quadrature modulation, a first amplifier that amplifies a modulation signal outputted by the quadrature modulator, and a second amplifier that amplifies an output signal of the first amplifier. The first amplifier operates as a limiter when the modulation format is the constant envelope modulation, and performs linear operation when the modulation format is the non-constant envelope modulation.
摘要翻译： 提供一种能够在不使用集成硬件的SAW滤波器的情况下降低噪声的发射机，并且应用恒定包络调制和非恒定包络调制的两种调制格式，以及使用发射机的小型化和低成本的无线通信装置 。 发射机包括通过正交调制来调制输入信号的正交调制器，放大由正交调制器输出的调制信号的第一放大器和放大第一放大器的输出信号的第二放大器。 当调制格式为恒定包络调制时，第一放大器用作限幅器，并且当调制格式是非恒定包络调制时，执行线性运算。
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公开(公告)号：US20050215222A1
公开(公告)日：2005-09-29
申请号：US11121018
申请日：2005-05-04
IPC分类号： H03L7/10 , H03D13/00 , H03L7/00 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/16 , H03L7/18 , H04B1/3822 , H04B1/40 , H04L7/033
CPC分类号： H03L7/10 , H03D13/007 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/12 , H04B1/406
摘要： In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.
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公开(公告)号：US20050176388A1
公开(公告)日：2005-08-11
申请号：US10509753
申请日：2003-02-18
CPC分类号： H03G3/3042 , H03F1/34 , H03F3/24 , H04B1/0475 , H04B2001/0433 , H04L27/361
摘要： In a transmitter of polar-loop architecture having a phase control loop and an amplitude control loop, as loop filters for controlling a loop band of the amplitude control loop, a first filter with lag-lead characteristics (secondary or more filter including a capacitor and a resistor) and a second filter of a perfect integrator type (filter including only a capacitor) are employed, and current-output type circuits are connected to respective front stages of the first and second filters.
摘要翻译： 在具有相位控制环路和幅度控制环路的极性环路架构的发射机中，作为用于控制振幅控制环路的环路频带的环路滤波器，具有滞后引线特性的第一滤波器（包括电容器和 电阻器）和完美积分器型（仅包括电容器的滤波器）的第二滤波器，并且电流输出型电路连接到第一和第二滤波器的各个前级。
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19.发明申请Communication semiconductor integrated circuit device and electrical apparatus 审中-公开通信半导体集成电路器件和电气设备公开(公告)号：US20050136847A1
公开(公告)日：2005-06-23
申请号：US11011153
申请日：2004-12-15
申请人： Hiroaki Matsui , Taizo Yamawaki , Masahiro Ito , Masakatsu Yokota
发明人： Hiroaki Matsui , Taizo Yamawaki , Masahiro Ito , Masakatsu Yokota
IPC分类号： H03G11/00 , H03F1/32 , H03F1/52 , H03F3/195 , H03F3/45 , H03F3/72 , H03G3/10 , H03G3/30 , H04B1/44
CPC分类号： H03F3/45286 , H03F1/3211 , H03F1/52 , H03F3/195 , H03F3/72 , H03F2200/09 , H03F2200/111 , H03F2203/45638 , H03F2203/45704 , H03F2203/45706 , H03G3/3042
摘要： A communication semiconductor integrated circuit (high frequency IC) that has a function of differentially-singly converts and outputs a transmitted signal suppressing deterioration of a harmonic suppression characteristic and enables miniaturization and an electronic component (high frequency module) that mounts the communication semiconductor integrated circuit are provided. In the communication semiconductor integrated circuit (high frequency IC) having a limiter that amplifies a modulated and up-converted transmitted signal and supplies a power amplifier with the signal, an unbalanced reduction means having, for example, differential MOS transistors is provided in collectors or drains of differential transistors that construct the limiter to output pins and continue to apply a current to the output pins and reduces the impedance of the transistor on an off side even when one of the transistors enters an off state in accordance with an input signal in parallel to the transistor.
摘要翻译： 具有差分单变换功能的通信用半导体集成电路（高频IC），输出抑制谐波抑制特性的劣化的发送信号，能够实现小型化，以及安装通信半导体集成电路的电子部件（高频模块） 被提供。 在具有放大经调制和上变频的发送信号并向功率放大器供给该信号的限幅器的通信半导体集成电路（高频IC）中，具有例如差分MOS晶体管的不平衡减小装置设置在收集器或 差分晶体管的漏极构成限制器以输出引脚并且继续向输出引脚施加电流，并且即使当晶体管中的一个根据并行的输入信号进入截止状态时也减小了晶体管在截止侧的阻抗 到晶体管。
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公开(公告)号：US20130049999A1
公开(公告)日：2013-02-28
申请号：US13338338
申请日：2011-12-28
申请人： TAKASHI OSHIMA , Taizo Yamawaki , Tomomi Takahashi
发明人： TAKASHI OSHIMA , Taizo Yamawaki , Tomomi Takahashi
IPC分类号： H03M1/10
CPC分类号： H03M1/1009 , H03M1/00 , H03M1/0695 , H03M1/1028 , H03M1/12 , H03M1/1215 , H03M1/804
摘要： A reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. Samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.
摘要翻译： 参考A / D转换单元并联连接到时间交织的A / D转换器的公共端作为校准对象，并且构成时间交织的A / D转换单元的每个单位A / D转换单元的输出， D转换器通过使用从参考A / D转换单元输出的低速高分辨率A / D转换结果在数字区域进行校准。 另外，fCLK / N（fCLK表示时间交织的A / D转换器的总体采样率，N是并行连接的单位A / D转换单元的数量的N相对于M）被设定为操作时钟频率 参考A / D转换单元。 所有单位A / D转换单元的采样可以与参考A / D转换单元的采样顺序同步，并且参考A / D转换器的工作时钟频率可以比总的采样率慢 时间交织的A / D转换器。
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