公开(公告)号：US07477715B2

公开(公告)日：2009-01-13

申请号：US11623925

申请日：2007-01-17

申请人： Young-Yong Byun ,  Dong-Jin Lee ,  Hi-Choon Lee

发明人： Young-Yong Byun ,  Dong-Jin Lee ,  Hi-Choon Lee

IPC分类号： H03D3/24

CPC分类号： H03L7/0814 ,  H03K5/13 ,  H03K2005/00052

摘要： A delay-locked loop (DLL) circuit includes a standby signal generating circuit, a front stage circuit, and a back stage circuit. The standby signal generating circuit generates a first standby signal and a second standby signal in response to an active signal, a crock enable signal, a first column address strobe (CAS) latency signal, and a second CAS latency signal. The front stage circuit compares the phase of an external clock signal and the phase of a feedback signal and delays the external clock signal based on the phase difference between the external clock signal and the feedback signal to generate a first clock signal. The back stage circuit executes interpolation and duty-cycle correction on the first clock signal.

摘要翻译： 延迟锁定环路（DLL）电路包括备用信号发生电路，前级电路和后级电路。 待机信号发生电路响应于有效信号，一个使能信号，一个第一列地址选通（CAS）等待时间信号和一个第二CAS等待时间信号，产生第一待机信号和第二备用信号。 前级电路将外部时钟信号的相位与反馈信号的相位进行比较，并且基于外部时钟信号和反馈信号之间的相位差来延迟外部时钟信号以产生第一时钟信号。 后级电路对第一时钟信号执行内插和占空比校正。

公开(公告)号：US20080204091A1

公开(公告)日：2008-08-28

申请号：US12072401

申请日：2008-02-26

申请人： Chul-Hwan Choo ,  Hi-Choon Lee ,  Young-Yong Byun

发明人： Chul-Hwan Choo ,  Hi-Choon Lee ,  Young-Yong Byun

IPC分类号： H03L7/08 ,  H01L23/12

CPC分类号： H03L7/0812 ,  G11C5/02 ,  G11C5/04 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/15311 ,  H03L7/0814 ,  H01L2224/0401

摘要： A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a DLL clock signal of a DLL circuit provided by the semiconductor chip having the DC generating circuits or provided by another semiconductor chip. Power consumption can be reduced, and sharing a DLL clock is valid. In addition, a stabilized DC supply can be guaranteed and an increase for level trimming range and productivity can be improved.

摘要翻译： 提供半导体芯片封装和半导体芯片制造方法。 半导体芯片封装包括至少两个具有堆叠结构的半导体芯片，所述半导体芯片至少一个：共享由所述半导体芯片中的一个提供的直流发电电路的直流信号; 并且共享由具有DC发生电路的半导体芯片提供或由另一半导体芯片提供的DLL电路的DLL电路的DLL时钟信号。 可以减少功耗，共享DLL时钟是有效的。 此外，可以保证稳定的DC电源，并且可以提高修整范围和生产率的增加。

公开(公告)号：US20080180149A1

公开(公告)日：2008-07-31

申请号：US12009080

申请日：2008-01-16

申请人： Young-yong Byun

发明人： Young-yong Byun

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/085 ,  H03L7/10

摘要： Provided are a DLL circuit having a coarse lock time adaptive to a frequency band of an external clock signal and a semiconductor memory device having the DLL circuit. The DLL circuit includes a delay circuit, a replica circuit, and a phase detector. The phase detector generates a first comparison signal used by the delay circuit to delay an external clock signal in units of a first cell delay time or a second comparison signal used by the delay circuit to delay the external clock signal in units of a second cell delay time. The DLL circuit delays the external clock signal by the cell delay time adaptive to the frequency band of the external clock signal, and thus can perform an accurate and rapid coarse lock operation for the entire frequency band.

摘要翻译： 提供一种具有适应于外部时钟信号的频带的粗略锁定时间的DLL电路和具有该DLL电路的半导体存储器件。 DLL电路包括延迟电路，复制电路和相位检测器。 相位检测器产生由延迟电路使用的第一比较信号，以以第一单元延迟时间为单位延迟外部时钟信号或延迟电路使用的第二比较信号，以以第二单元延迟为单位延迟外部时钟信号 时间。 DLL电路将外部时钟信号延迟自适应外部时钟信号的频带的单元延迟时间，从而可以对整个频带执行准确和快速的粗略锁定操作。

公开(公告)号：US20070176657A1

公开(公告)日：2007-08-02

申请号：US11623925

申请日：2007-01-17

申请人： Young-Yong Byun ,  Dong-Jin Lee ,  Hi-Choon Lee

发明人： Young-Yong Byun ,  Dong-Jin Lee ,  Hi-Choon Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/13 ,  H03K2005/00052

摘要： A delay-locked loop (DLL) circuit includes a standby signal generating circuit, a front stage circuit, and a back stage circuit. The standby signal generating circuit generates a first standby signal and a second standby signal in response to an active signal, a crock enable signal, a first column address strobe (CAS) latency signal, and a second CAS latency signal. The front stage circuit compares the phase of an external clock signal and the phase of a feedback signal and delays the external clock signal based on the phase difference between the external clock signal and the feedback signal to generate a first clock signal. The back stage circuit executes interpolation and duty-cycle correction on the first clock signal.

摘要翻译： 延迟锁定环路（DLL）电路包括备用信号发生电路，前级电路和后级电路。 待机信号发生电路响应于有效信号，一个使能信号，一个第一列地址选通（CAS）等待时间信号和一个第二CAS等待时间信号，产生第一待机信号和第二备用信号。 前级电路将外部时钟信号的相位与反馈信号的相位进行比较，并且基于外部时钟信号和反馈信号之间的相位差来延迟外部时钟信号以产生第一时钟信号。 后级电路对第一时钟信号执行内插和占空比校正。