公开(公告)号：US07734003B2

公开(公告)日：2010-06-08

申请号：US12136186

申请日：2008-06-10

申请人： Chih-Yuan Chien ,  Yu-Ju Kuo ,  Wan-Jung Chen

发明人： Chih-Yuan Chien ,  Yu-Ju Kuo ,  Wan-Jung Chen

IPC分类号： G11C19/00

CPC分类号： G11C19/28

摘要： A shift register array is provided. The shift register array includes a plurality of shift registers connected in serial. The shift register includes a first transistor coupled between a first input terminal and a first node, a second transistor coupled between a first clock input terminal and an output terminal and a pull-up unit. The first transistor has a gate coupled to the first input terminal. The second transistor has a gate coupled to the first node. The pull-up unit includes a third transistor coupled between the first node and a ground, a capacitor coupled between the first clock input terminal and the second node and a fourth transistor coupled between the second node and the ground. The third transistor has a gate coupled to a second node. The fourth transistor has a gate coupled to the first node.

摘要翻译： 提供了移位寄存器阵列。 移位寄存器阵列包括串联连接的多个移位寄存器。 移位寄存器包括耦合在第一输入端和第一节点之间的第一晶体管，耦合在第一时钟输入端和输出端之间的第二晶体管和上拉单元。 第一晶体管具有耦合到第一输入端的栅极。 第二晶体管具有耦合到第一节点的栅极。 上拉单元包括耦合在第一节点和地之间的第三晶体管，耦合在第一时钟输入端和第二节点之间的电容器以及耦合在第二节点和地之间的第四晶体管。 第三晶体管具有耦合到第二节点的栅极。 第四晶体管具有耦合到第一节点的栅极。

公开(公告)号：US20080042965A1

公开(公告)日：2008-02-21

申请号：US11763040

申请日：2007-06-14

申请人： Kuo-hsing Cheng ,  Ming-sheng Lai ,  Chih-yuan Chien ,  Yu-ju Kuo

发明人： Kuo-hsing Cheng ,  Ming-sheng Lai ,  Chih-yuan Chien ,  Yu-ju Kuo

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G09G2330/04 ,  G11C19/28

摘要： A shift register unit includes a plurality of register units electrically coupled in cascade. Each register unit outputs an output pulse according to a first clock signal, a second clock signal and an output pulse of a previous register unit. Each register unit includes a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, and a driving unit. The first switch unit is used for conducting the input pulse to a first node when the first switch is turned on. The second switch unit is used for conducting the output pulse of the register unit according to the first clock signal to an output end when the second switch unit is turned on in response to the input pulse. The third switch unit electrically coupled to a supply end is used for conducting a supply voltage to the output end when the second switch unit is turned off. The fourth switch unit electrically coupled to the supply end is used for conducting the supply voltage to the first node when the fourth switch unit is turned on in response to a driving pulse. The driving unit is used for providing the driving pulse according to the first clock signal, the second clock signal, and the input pulse.

摘要翻译： 移位寄存器单元包括级联电耦合的多个寄存器单元。 每个寄存器单元根据第一时钟信号，第二时钟信号和先前寄存器单元的输出脉冲输出输出脉冲。 每个寄存单元包括第一开关单元，第二开关单元，第三开关单元，第四开关单元和驱动单元。 当第一开关接通时，第一开关单元用于将输入脉冲传导到第一节点。 当第二开关单元响应于输入脉冲而导通时，第二开关单元用于根据第一时钟信号将寄存器单元的输出脉冲传导到输出端。 电耦合到供电端的第三开关单元用于当第二开关单元断开时将电源电压输送到输出端。 电耦合到供电端的第四开关单元用于当第四开关单元响应于驱动脉冲接通时，将电源电压传导到第一节点。 驱动单元用于根据第一时钟信号，第二时钟信号和输入脉冲提供驱动脉冲。

公开(公告)号：US07928942B2

公开(公告)日：2011-04-19

申请号：US11846383

申请日：2007-08-28

申请人： Yu-ju Kuo ,  Ming-sheng Lai ,  Kuo-hsing Cheng ,  Chih-yuan Chien

发明人： Yu-ju Kuo ,  Ming-sheng Lai ,  Kuo-hsing Cheng ,  Chih-yuan Chien

IPC分类号： G09G3/36

CPC分类号： G11C19/28 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0417 ,  G09G2320/0223

摘要： A signal-driving system for constructing gate signals of liquid crystal display (LCD), includes a plural stage of cascaded shift register units. Each stage of shift register unit includes a first pull-up switch unit, which is turned on for outputting a gate pulse on an output of this stage, based on either the first clock signal or the second clock signal; a pull-up driving unit, which is used for providing a driving pulse via a node for driving the first pull-up switch unit; a first pull-down switch unit, which is turned on to connect the output to a low-level voltage source; a second pull-down switch unit, which is turned on to connect said node to the low-level voltage source; a carry buffer unit, which is used for providing a control pulse on the second pull-down switch unit of previous stage, based on either the first clock signal or the second clock signal, and thereby ensuring operation of each stage independent of gate pulse signals outputted from the other stages.

摘要翻译： 用于构成液晶显示器（LCD）的门信号的信号驱动系统包括多级级联移位寄存器单元。 移位寄存器单元的每个级包括第一上拉开关单元，其基于第一时钟信号或第二时钟信号而被导通以输出该级输出上的门脉冲; 上拉驱动单元，用于经由用于驱动第一上拉开关单元的节点提供驱动脉冲; 第一下拉开关单元，其被接通以将输出连接到低电平电压源; 第二下拉开关单元，其被接通以将所述节点连接到所述低电平电压源; 进位缓冲单元，用于基于第一时钟信号或第二时钟信号在前一级的第二下拉开关单元上提供控制脉冲，从而确保每个级的操作独立于门脉冲信号 从其他阶段输出。

公开(公告)号：US20090041177A1

公开(公告)日：2009-02-12

申请号：US12136186

申请日：2008-06-10

申请人： Chih-Yuan CHIEN ,  Yu-Ju KUO ,  Wan-Jung CHEN

发明人： Chih-Yuan CHIEN ,  Yu-Ju KUO ,  Wan-Jung CHEN

IPC分类号： G11C19/00

CPC分类号： G11C19/28

摘要： A shift register array is provided. The shift register array includes a plurality of shift registers connected in serial. The shift register includes a first transistor coupled between a first input terminal and a first node, a second transistor coupled between a first clock input terminal and an output terminal and a pull-up unit. The first transistor has a gate coupled to the first input terminal. The second transistor has a gate coupled to the first node. The pull-up unit includes a third transistor coupled between the first node and a ground, a capacitor coupled between the first clock input terminal and the second node and a fourth transistor coupled between the second node and the ground. The third transistor has a gate coupled to a second node. The fourth transistor has a gate coupled to the first node.

摘要翻译： 提供了移位寄存器阵列。 移位寄存器阵列包括串联连接的多个移位寄存器。 移位寄存器包括耦合在第一输入端和第一节点之间的第一晶体管，耦合在第一时钟输入端和输出端之间的第二晶体管和上拉单元。 第一晶体管具有耦合到第一输入端的栅极。 第二晶体管具有耦合到第一节点的栅极。 上拉单元包括耦合在第一节点和地之间的第三晶体管，耦合在第一时钟输入端和第二节点之间的电容器以及耦合在第二节点和地之间的第四晶体管。 第三晶体管具有耦合到第二节点的栅极。 第四晶体管具有耦合到第一节点的栅极。