Abstract:
A receiver of a magnetic resonance imaging system and a magnetic resonance imaging system are provided. The receiver includes a receiving end for receiving an analog magnetic resonance signal from a local coil of the magnetic resonance imaging system, a sending end for sending a digital magnetic resonance signal to an image reconstruction apparatus of the magnetic resonance imaging system, at least two digital processing channels connected to the sending end for digitizing the analog magnetic resonance signal to the digital magnetic resonance signal, and a channel selection unit connected between the digital processing channels and the receiving end for selecting a corresponding digital processing channel from the digital processing channels according to type information about the local coil. The embodiments may be compatible with many types of local coils without re-designing the local coils, which significantly reduces the cost of the system.
Abstract:
An RF coil device and an MRI apparatus allowing a connection relationship between input RF channels and output RF channels to be controlled by a smaller number of switch elements are provided. The RF coil device includes multiple coil segments and a multi-selection switch. Input terminals of the multi-selection switch are each connected to a different coil segment. An output terminal of the multi-selection switch leads to an RF output channel. A control terminal of the multi-selection switch is used to receive a control signal so as to select a coil segment for connection to the output terminal. Multiple coil segments connected to the input terminals are not in consecutive positions, and the number of coil segments by which any two of the multiple coil segments are spaced apart is no fewer than the maximum number of coil segments required for one MRI imaging less 1. The MRI apparatus includes the RF coil device.
Abstract:
Various embodiments of the present invention are related to memory buffers, and in particular to a multi-write bit-fill FIFO to which multiple addresses may be written simultaneously and which fills in bit spaces as data blocks are written.