公开(公告)号：US5726595A

公开(公告)日：1998-03-10

申请号：US745270

申请日：1996-11-08

Applicant: Allan Lin ,  L. Vincent Xie

Inventor： Allan Lin ,  L. Vincent Xie

IPC: G06F1/10 ,  H04L7/027 ,  H04L7/02

CPC classification number: H04L7/027 ,  G06F1/10

Abstract: A circuit is for re-synchronizing an event indication signal received from a foreign domain to generate a result indication signal that is re-synchronized to a host clock signal. The event indication signal is received from the foreign domain at a first input terminal; and a host clock signal is received at a second input terminal. Edge-triggered flip flop circuitry of the circuit has a clock input, a data input, and a data output. The clock input is coupled to the second input terminal and the data input is coupled to receive a latch output signal. The edge-triggered flip flop circuitry clocks the latch output signal to the data output of the flip flop circuitry, to generate a result event indication signal, in response to a transition in the host clock signal. Delay circuitry is coupled to the first input terminal to receive the event indication signal. The delay circuitry provides a delayed event indication signal having a phase that is delayed from the event indication signal. Transparent latch circuitry latches the delayed event indication signal responsive to a latch control signal, and combination circuitry is coupled to receive the event indication signal and the result event indication signal, and provides a combination thereof as the latch control signal.

Abstract translation: 电路用于重新同步从外部域接收到的事件指示信号，以产生与主机时钟信号重新同步的结果指示信号。 在第一输入端从外界接收事件指示信号; 并且在第二输入端接收主机时钟信号。 电路的边沿触发触发器电路具有时钟输入，数据输入和数据输出。 时钟输入耦合到第二输入端，并且数据输入被耦合以接收锁存输出信号。 边沿触发的触发器电路将锁存器输出信号时钟反馈到触发器电路的数据输出，以响应于主机时钟信号中的转换而产生结果事件指示信号。 延迟电路耦合到第一输入端以接收事件指示信号。 延迟电路提供具有从事件指示信号延迟的相位的延迟事件指示信号。 透明锁存电路响应锁存控制信号锁存延迟事件指示信号，并且组合电路被耦合以接收事件指示信号和结果事件指示信号，并提供其组合作为锁存控制信号。