公开(公告)号：US08671303B2

公开(公告)日：2014-03-11

申请号：US13349228

申请日：2012-01-12

申请人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

发明人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/222

摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

摘要翻译： 用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。 通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。 在一个示例性校准例程中，向接收设备提供时钟信号。 还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。 然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。 每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

公开(公告)号：US08122275B2

公开(公告)日：2012-02-21

申请号：US11843123

申请日：2007-08-22

申请人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

发明人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/222

摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

摘要翻译： 用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。 通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。 在一个示例性校准例程中，向接收设备提供时钟信号。 还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。 然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。 每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

公开(公告)号：US07706996B2

公开(公告)日：2010-04-27

申请号：US11735394

申请日：2007-04-13

申请人： Yan Chong ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

发明人： Yan Chong ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

IPC分类号： G06F11/00 ,  G06F19/00

CPC分类号： G06F13/4213

摘要： Circuits, methods and apparatus are provided to reduce skew among signals being provided or transmitted by a data interface. Signal path delays are varied such that signals transmitted by a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration, external circuitry, or design tools can provide skew adjustment of each output channel by determining one or more delays for each output channel path. When aligning multiple edges, the edges of the output signals may be aligned independently, e.g., using edge specific delay elements.

摘要翻译： 提供电路，方法和装置以减少由数据接口提供或发送的信号之间的偏差。 信号路径延迟是变化的，使得由存储器接口发送的信号沿着上升沿和/或下降沿彼此校准或对齐。 例如，自校准，外部电路或设计工具可以通过确定每个输出通道路径的一个或多个延迟来提供每个输出通道的偏移调整。 当对准多个边缘时，输出信号的边缘可以独立对准，例如使用边缘特定的延迟元件。

公开(公告)号：US07509223B2

公开(公告)日：2009-03-24

申请号：US11735386

申请日：2007-04-13

申请人： Yan Chong ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

发明人： Yan Chong ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

IPC分类号： G06F3/00

CPC分类号： G01R31/31922 ,  G01R31/3191 ,  G01R31/31937 ,  H04L7/0008 ,  H04L7/0041

摘要： Circuits, methods and apparatus are provided to reduce skew among signals being received by a data interface. Signal path delays are varied such that data and strobe signals received at a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration circuitry provides skew adjustment of each data signal path by determining one or more delays in each data signal path and strobe signal path based on relative timings of test signals. The rising or falling edges may be used for this alignment.

摘要翻译： 提供电路，方法和装置以减少由数据接口接收的信号之间的偏差。 变化信号路径延迟使得在存储器接口处接收的数据和选通信号沿着上升沿和/或下降沿彼此校准或对齐。 例如，自校准电路通过基于测试信号的相对定时确定每个数据信号路径和选通信号路径中的一个或多个延迟来提供每个数据信号路径的偏移调整。 上升或下降沿可用于此对齐。

公开(公告)号：US09558131B1

公开(公告)日：2017-01-31

申请号：US13164426

申请日：2011-06-20

申请人： Jeffrey Schulz ,  Chiakang Sung ,  Michael H. M. Chu

发明人： Jeffrey Schulz ,  Chiakang Sung ,  Michael H. M. Chu

IPC分类号： G06F13/00

CPC分类号： G06F13/00 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/4022

摘要： An IC that includes a first memory controller, a second memory controller, and a first bonding circuit coupled to the first memory controller, where the first bonding circuit is a hard logic bonding circuit and is operable to coordinate memory control functions of the first memory controller and the second memory controller. In one implementation, the first memory controller is an N bits wide memory controller, the second memory controller is an M bits wide memory controller, and the first bonding circuit is operable to coordinate the memory control functions of the first memory controller and the second memory controller such that the first and second memory controllers together function as an N+M bits wide memory controller, where N and M are positive integers.

摘要翻译： 一种IC，包括第一存储器控制器，第二存储器控制器和耦合到第一存储器控制器的第一接合电路，其中第一接合电路是硬逻辑接合电路，并且可操作以协调第一存储器控制器的存储器控​​制功能 和第二存储器控制器。 在一个实现中，第一存储器控制器是N位宽存储器控制器，第二存储器控制器是M位宽存储器控制器，并且第一接合电路可操作以协调第一存储器控制器和第二存储器的存储器控​​制功能 控制器，使得第一和第二存储器控制器一起用作N + M位宽存储器控制器，其中N和M是正整数。

公开(公告)号：US09032162B1

公开(公告)日：2015-05-12

申请号：US13209137

申请日：2011-08-12

申请人： Ching-Chi Chang ,  Ravish Kapasi ,  Jeffrey Schulz ,  Michael H. M. Chu ,  Caroline Ssu-Min Chen ,  Chiakang Sung

发明人： Ching-Chi Chang ,  Ravish Kapasi ,  Jeffrey Schulz ,  Michael H. M. Chu ,  Caroline Ssu-Min Chen ,  Chiakang Sung

IPC分类号： G11C7/10

CPC分类号： G11C7/1075 ,  G06F13/161

摘要： An integrated circuit may include a memory controller serving as an interface between master processing modules and system memory. The master processing modules may provide memory access requests to the memory controller along with respective tag identifications. The memory controller may place the memory access requests in a queue for fulfillment. The memory controller may include a merging module that generates a memory access request to replace two or more memory access requests previously received from the master processing modules. The merging module may store information associated with the memory access requests that were merged and use the stored information to assign appropriate tag identifications to portions of data obtained from system memory when fulfilling the generated memory access request. The memory controller may include a verification module that can be used with test equipment to optimize the design of the master processing modules for improved memory access performance.

摘要翻译： 集成电路可以包括用作主处理模块和系统存储器之间的接口的存储器控​​制器。 主处理模块可以向存储器控制器提供存储器访问请求以及相应的标签标识。 存储器控制器可以将存储器访问请求放置在队列中以实现。 存储器控制器可以包括合并模块，其生成存储器访问请求以替换先前从主处理模块接收的两个或多个存储器访问请求。 合并模块可以存储与被合并的存储器访问请求相关联的信息，并使用所存储的信息，以在满足生成的存储器访问请求时从系统存储器获得的数据部分分配适当的标签标识。 存储器控制器可以包括可与测试设备一起使用的验证模块，以优化主处理模块的设计以改善存储器访问性能。

公开(公告)号：US09343124B1

公开(公告)日：2016-05-17

申请号：US13194842

申请日：2011-07-29

申请人： Caroline Ssu-Min Chen ,  Jeffrey Schulz ,  Michael H. M. Chu ,  Ravish Kapasi

发明人： Caroline Ssu-Min Chen ,  Jeffrey Schulz ,  Michael H. M. Chu ,  Ravish Kapasi

IPC分类号： G06F12/00 ,  G11C7/10 ,  G06F12/08

CPC分类号： G11C7/1075 ,  G06F12/0853

摘要： A method and system for operating a multi-port memory system are disclosed. A memory controller may service read requests by accessing requested data from an external memory and communicating it to the requesting memory ports for access by devices coupled to the memory ports. A shared memory of the memory controller may be used to temporarily store data if a buffer associated with a requesting device is full. To reduce the ability for a slower memory port to occupy the shared memory and cause faster memory ports to be underserviced, the memory controller may advantageously regulate or limit issuance of read requests by memory ports operating at slower clock frequencies. The memory ports may be regulated independently of one another based on at least one respective attribute of each memory port, at least one attribute of the external memory, etc.

摘要翻译： 公开了一种用于操作多端口存储器系统的方法和系统。 存储器控制器可以通过从外部存储器访问所请求的数据并将其传送到请求存储器端口来服务读取请求以供由耦合到存储器端口的设备访问。 如果与请求设备相关联的缓冲器已满，则可以使用存储器控制器的共享存储器临时存储数据。 为了减少较慢的存储器端口占用共享存储器并导致更快的存储器端口不足的能力，存储器控制器可以有利地调节或限制以更慢的时钟频率操作的存储器端口发出读取请求。 存储器端口可以基于每个存储器端口的至少一个相应属性，外部存储器的至少一个属性等彼此独立地被调整。

公开(公告)号：US09208109B2

公开(公告)日：2015-12-08

申请号：US13151101

申请日：2011-06-01

申请人： Michael H. M. Chu ,  Jeffrey Schulz ,  Chiakang Sung ,  Ravish Kapasi

发明人： Michael H. M. Chu ,  Jeffrey Schulz ,  Chiakang Sung ,  Ravish Kapasi

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/18

CPC分类号： G06F13/1626 ,  G06F13/16 ,  G06F13/1605 ,  G06F13/18

摘要： A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have associated priority values and fulfill the memory access requests by configuring system memory to respond to the memory access requests. To dynamically modify the associated priority values while the memory controller receives and fulfills the memory access requests, a priority value update module may be provided that dynamically updates priority values for the memory controller ports. The priority value update module may provide the updated priority values with update registers that are updated based on an update signal and a system clock. The priority values may be provided by shift registers, memory mapped registers, or provided by masters along with each memory access request.

摘要翻译： 可编程集成电路可以具有在主模块和系统存储器之间进行接口的存储器控​​制器。 存储器控制器可以通过具有相关优先级值的端口从主设备接收存储器访问请求，并通过配置系统存储器来响应存储器访问请求来满足存储器访问请求。 为了在存储器控制器接收并满足存储器访问请求的同时动态地修改相关联的优先级值，可以提供动态地更新存储器控制器端口的优先级值的优先级值更新模块。 优先级值更新模块可以根据更新信号和系统时钟向更新的优先级值提供更新的更新寄存器。 优先级值可以由移位寄存器，存储器映射寄存器提供，或由主器件与每个存储器访问请求一起提供。