公开(公告)号：US09883822B2

公开(公告)日：2018-02-06

申请号：US15181229

申请日：2016-06-13

申请人： Apple Inc.

发明人： Milind S. Bhagavat ,  Jun Zhai

IPC分类号： G06K9/00 ,  A61B5/117 ,  A61B5/1172 ,  A61B5/053 ,  H01L27/146

CPC分类号： A61B5/1172 ,  A61B5/053 ,  A61B2562/0214 ,  A61B2562/182 ,  G06K9/0002 ,  H01L27/14634 ,  H01L27/14636

摘要： A sensor includes a sensor array formed on a first side of a substrate and at least one circuit operative to communicate with the sensor array formed on a second side of the substrate. At least one via extends through the substrate to electrically connect the sensor array to the at least one circuit. Placing the at least one circuit on the second side of the substrate allows the sensor array to occupy substantially all of the first side of the substrate.

公开(公告)号：US20170156002A1

公开(公告)日：2017-06-01

申请号：US15005908

申请日：2016-01-25

申请人： Apple Inc.

发明人： Caleb C. Han ,  Jun Zhai ,  Tongbi T. Jiang

IPC分类号： H04R1/14 ,  H04R31/00 ,  H04R1/10 ,  H04R19/00 ,  H04R19/04

CPC分类号： H04R1/14 ,  H04R1/04 ,  H04R1/1041 ,  H04R1/46 ,  H04R19/005 ,  H04R19/04 ,  H04R31/006 ,  H04R2201/107

摘要： MEMS microphone and vibration sensor dies and packages are described. In an embodiment, a MEMS microphone and vibration sensor die includes a die substrate, a MEMS microphone on the die substrate and a MEMS vibration sensor on the die substrate. The MEMS vibration sensor may include a plurality of beams with different proof masses corresponding to different resonant frequencies, wherein the different proof masses comprise a same material as the die substrate.

公开(公告)号：US09661411B1

公开(公告)日：2017-05-23

申请号：US15005908

申请日：2016-01-25

申请人： Apple Inc.

发明人： Caleb C. Han ,  Jun Zhai ,  Tongbi T. Jiang

IPC分类号： H04R1/14 ,  H04R19/00 ,  H04R19/04 ,  H04R1/10 ,  H04R31/00

CPC分类号： H04R1/14 ,  H04R1/04 ,  H04R1/1041 ,  H04R1/46 ,  H04R19/005 ,  H04R19/04 ,  H04R31/006 ,  H04R2201/107

摘要： MEMS microphone and vibration sensor dies and packages are described. In an embodiment, a MEMS microphone and vibration sensor die includes a die substrate, a MEMS microphone on the die substrate and a MEMS vibration sensor on the die substrate. The MEMS vibration sensor may include a plurality of beams with different proof masses corresponding to different resonant frequencies, wherein the different proof masses comprise a same material as the die substrate.

公开(公告)号：US20170141088A1

公开(公告)日：2017-05-18

申请号：US15405046

申请日：2017-01-12

申请人： Apple Inc.

发明人： Jun Zhai ,  Kunzhong Hu

IPC分类号： H01L25/10 ,  H01L23/31 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56

CPC分类号： H01L25/105 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/82005 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83101 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/1451 ,  H01L2924/14511 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/19

摘要： Vertically stacked system in package structures are described. In an embodiment, a package includes a first level molding and fan out structure, a third level molding and fan out structure, and a second level molding and fan out structure between the first and third levels. The second level molding and fan out structure includes back-to-back facing die, with a front surface of each die bonded to a redistribution layer.

公开(公告)号：US09559081B1

公开(公告)日：2017-01-31

申请号：US14935310

申请日：2015-11-06

申请人： Apple Inc.

发明人： Kwan-Yu Lai ,  Jun Zhai ,  Kunzhong Hu

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00 ,  H01L23/00 ,  H01L21/768

CPC分类号： H01L25/0657 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7684 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/10 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/181 ,  H01L2924/186

摘要： Packages and 3D die stacking processes are described. In an embodiment, a package includes a second level die hybrid bonded to a first package level including a first level die encapsulated in an oxide layer, and a plurality of through oxide vias (TOVs) extending through the oxide layer. In an embodiment, the TOVs and the first level die have a height of about 20 microns or less.

摘要翻译： 描述了封装和3D裸片堆叠过程。 在一个实施例中，封装包括结合到包括封装在氧化物层中的第一级管芯的第一封装级的第二级管芯晶体管和延伸穿过氧化物层的多个通孔氧化物通孔（TOV）。 在一个实施例中，TOV和第一级模具具有大约20微米或更小的高度。

公开(公告)号：US09548288B1

公开(公告)日：2017-01-17

申请号：US14966482

申请日：2015-12-11

申请人： Apple Inc.

发明人： Vidhya Ramachandran ,  Chonghua Zhong ,  Shawn Searles ,  Jun Zhai ,  Young Doo Jeon ,  Huabo Chen

IPC分类号： H01L25/16 ,  H01L23/528 ,  H01L23/50 ,  H01L21/78 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

CPC分类号： H01L25/16 ,  H01L21/768 ,  H01L21/78 ,  H01L23/50 ,  H01L23/528 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/16265 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1427 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/145 ,  H01L2924/14511 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2224/81

摘要： A system that includes an integrated circuit die and a power supply decoupling unit is disclosed. The system includes an integrated circuit die, and interconnection region, and a decoupling unit. The integrated circuit die includes a plurality of circuits, which each include multiple devices interconnected using wires fabricated on a first plurality of conductive layers. The interconnection region includes multiple solder balls, and multiple conductive paths, each of which includes wires fabricated on a second plurality conductive layers. At least one solder ball is connected to an Input/Output terminal of a first circuit of the plurality of circuits via one of the conductive paths. The decoupling unit may include a plurality of capacitors and a plurality of terminals. Each terminal of the decoupling unit may be coupled to a respective power terminal of a second circuit of the plurality of circuits via the conductive paths.

摘要翻译： 公开了一种包括集成电路管芯和电源去耦单元的系统。 该系统包括集成电路管芯和互连区域以及去耦单元。 集成电路管芯包括多个电路，每个电路包括使用在第一多个导电层上制造的导线互连的多个器件。 互连区域包括多个焊球，以及多个导电路径，每个导电路径包括制造在第二多个导电层上的导线。 至少一个焊球通过导电路径之一连接到多个电路中的第一电路的输入/输出端子。 去耦单元可以包括多个电容器和多个端子。 去耦单元的每个端子可以经由导电路径耦合到多个电路中的第二电路的相应电源端子。

公开(公告)号：US20160358889A1

公开(公告)日：2016-12-08

申请号：US14730171

申请日：2015-06-03

申请人： Apple Inc.

发明人： Kwan-Yu Lai ,  Jun Zhai ,  Kunzhong Hu ,  Flynn P. Carson

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56 ,  H01L25/00 ,  H01L23/48 ,  H01L23/528

CPC分类号： H01L21/768 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106

摘要： Packages including an embedded die with through silicon vias (TSVs) are described. In an embodiment, a first level die including TSVs is embedded between a first redistribution layer (RDL) and a second RDL, and a second level die is mounted on a top side of the first redistribution layer. In an embodiment, the first level die is an active die, less than 50 μm thick.

摘要翻译： 描述了包括通过硅通孔（TSV）的嵌入式裸片的封装。 在一个实施例中，包括TSV的第一级裸片被嵌入在第一重分配层（RDL）和第二RDL之间，并且第二级管芯安装在第一再分布层的顶侧。 在一个实施例中，第一级模具是小于50μm厚的有源管芯。

公开(公告)号：US20160217311A1

公开(公告)日：2016-07-28

申请号：US15090474

申请日：2016-04-04

申请人： Apple Inc.

发明人： Milind S. Bhagavat ,  Jun Zhai

IPC分类号： G06K9/00

CPC分类号： G06K9/0002 ,  H01L27/14634 ,  H01L27/14636

摘要： A sensor includes a sensor array formed on a first side of a substrate and at least one circuit operative to communicate with the sensor array formed on a second side of the substrate. At least one via extends through the substrate to electrically connect the sensor array to the at least one circuit. Placing the at least one circuit on the second side of the substrate allows the sensor array to occupy substantially all of the first side of the substrate.

摘要翻译： 传感器包括形成在基板的第一侧上的传感器阵列和至少一个可操作地与形成在基板的第二侧上的传感器阵列通信的电路。 至少一个通孔延伸穿过衬底以将传感器阵列电连接到至少一个电路。 将至少一个电路放置在基板的第二侧上，使得传感器阵列基本上占据基板的所有第一侧。

公开(公告)号：US20160172261A1

公开(公告)日：2016-06-16

申请号：US15050110

申请日：2016-02-22

申请人： Apple Inc.

发明人： Jun Chung Hsu ,  Jun Zhai

IPC分类号： H01L23/13 ,  H01L23/498 ,  H01L25/065 ,  H01L23/48

CPC分类号： H01L23/13 ,  H01L21/4857 ,  H01L21/76802 ,  H01L23/12 ,  H01L23/481 ,  H01L23/49822 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/19106 ,  H01L2924/00

摘要： A bottom package for a PoP (package-on-package) may be formed with a reinforcement layer supporting a thin or coreless substrate. The reinforcement layer may provide stiffness and rigidity to the substrate to increase the stiffness and rigidity of the bottom package and provide better handling of the substrate. The reinforcement layer may be formed using core material, a laminate layer, and a metal layer. The substrate may be formed on the reinforcement layer. The reinforcement layer may include an opening sized to accommodate a die. The die may be coupled to an exposed surface of the substrate in the opening. Metal filled vias through the reinforcement layer may be used to couple the substrate to a top package.

公开(公告)号：US09331058B2

公开(公告)日：2016-05-03

申请号：US14097491

申请日：2013-12-05

申请人： Apple Inc.

发明人： John Bruno ,  Jun Zhai ,  Timothy J. Millet

IPC分类号： H05K7/20 ,  H01L25/16 ,  H01L23/13 ,  H01L23/367 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18

CPC分类号： H01L25/18 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/13124 ,  H01L2224/134 ,  H01L2224/13411 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0204 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/09036 ,  H05K2201/10416 ,  H05K2201/10734 ,  H01L2924/014

摘要： A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The processor die and the memory die are coupled to opposite sides of the BGA substrate using terminals (e.g., solder balls). The package may be coupled to a printed circuit board (PCB) using one or more terminals positioned around the perimeter of the processor die. The PCB may include a recess with at least part of the processor die being positioned in the recess. Positioning at least part of the processor die in the recess reduces the overall height of the semiconductor package assembly. A voltage regulator may also be coupled to the BGA substrate on the same side as the processor die with at least part of the voltage regulator being positioned in the recess a few millimeters from the processor die.

摘要翻译： 半导体封装包括耦合到球栅阵列（BGA）衬底的处理器管芯（例如，SoC）和一个或多个存储器管芯（例如，DRAM）。 使用端子（例如，焊球）将处理器管芯和存储器管芯耦合到BGA衬底的相对侧。 可以使用位于处理器管芯的周边周围的一个或多个端子将封装耦合到印刷电路板（PCB）。 PCB可以包括凹部，其中处理器管芯的至少一部分位于凹部中。 将处理器管芯的至少一部分定位在凹部中减小了半导体封装组件的整体高度。 电压调节器还可以与处理器管芯相同侧的BGA衬底耦合，其中至少一部分电压调节器位于距离处理器管芯几毫米的凹槽中。