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公开(公告)号：US10176551B2
公开(公告)日：2019-01-08
申请号：US15499543
申请日：2017-04-27
Applicant: Apple Inc.
Inventor： Sung Hee Park , Muge Wang , Junji Sugisawa
Abstract: Embodiments relate to a configurable convolution engine that receives configuration information to perform convolution and other deep machine learning operations on streaming input data of various formats. The convolution engine may include two convolution circuits that each generate a stream of values by applying convolution kernels to input data. The stream of values may each define one or more channels of image data. A channel merge circuit combines the streams of values from each convolution circuit in accordance with a selected mode of operation. In one mode, the first and second streams from the convolution circuits are merged into an output stream having the combined channels of the first and second streams in an interleaved manner. In another mode, the first stream from the first convolution circuit is fed into the input of the second convolution circuit.
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公开(公告)号：US20180315155A1
公开(公告)日：2018-11-01
申请号：US15499543
申请日：2017-04-27
Applicant: Apple Inc.
Inventor： Sung Hee Park , Muge Wang , Junji Sugisawa
CPC classification number: G06T1/20 , G06F17/153 , G06K9/00986 , G06K9/4628 , G06K9/4647 , G06N3/063 , G06T5/001 , G06T5/20
Abstract: Embodiments relate to a configurable convolution engine that receives configuration information to perform convolution and other deep machine learning operations on streaming input data of various formats. The convolution engine may include two convolution circuits that each generate a stream of values by applying convolution kernels to input data. The stream of values may each define one or more channels of image data. A channel merge circuit combines the streams of values from each convolution circuit in accordance with a selected mode of operation. In one mode, the first and second streams from the convolution circuits are merged into an output stream having the combined channels of the first and second streams in an interleaved manner. In another mode, the first stream from the first convolution circuit is fed into the input of the second convolution circuit.
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公开(公告)号：US20180082400A1
公开(公告)日：2018-03-22
申请号：US15823292
申请日：2017-11-27
Applicant: Apple Inc.
Inventor： Suk Hwan Lim , Junji Sugisawa , Muge Wang
CPC classification number: G06F17/153 , G06T5/001 , G06T5/20
Abstract: Embodiments of the present disclosure relate to a configurable convolution engine that receives configuration information to perform convolution or its variant operations on streaming input data of various formats. To process streaming input data, input data of multiple channels are received and stored in an input buffer circuit in an interleaved manner. Data values of the interleaved input data are retrieved and forwarded to multiplier circuits where multiplication with a corresponding filter element of a kernel is performed. Varying number of kernels with different sizes and sparsity can also be used for the convolution operations.
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公开(公告)号：US09858636B1
公开(公告)日：2018-01-02
申请号：US15198478
申请日：2016-06-30
Applicant: Apple Inc.
Inventor： Suk Hwan Lim , Junji Sugisawa , Muge Wang
CPC classification number: G06F17/153
Abstract: Embodiments of the present disclosure relate to a configurable convolution engine that receives configuration information to perform convolution or its variant operations on streaming input data of various formats. To process streaming input data, input data of multiple channels are received and stored in an input buffer circuit in an interleaved manner. Data values of the interleaved input data are retrieved and forwarded to multiplier circuits where multiplication with a corresponding filter element of a kernel is performed. Varying number of kernels with different sizes and sparsity can also be used for the convolution operations.
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