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    Methods of forming hardmasks
    13.
    发明授权
    Methods of forming hardmasks 有权

    公开(公告)号：US11699585B2

    公开(公告)日：2023-07-11

    申请号：US17075967

    申请日：2020-10-21

    Applicant: Applied Materials, Inc.

    Inventor： Jui-Yuan Hsu ,  Pramit Manna ,  Bhaskar Kumar ,  Karthik Janakiraman

    IPC: H01L21/02 ,  H01L21/033

    CPC classification number: H01L21/0234 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/0332

    Abstract: Embodiments of the present disclosure generally relate to methods of forming hardmasks. Embodiments described herein enable, e.g., formation of carbon-containing hardmasks having reduced film stress. In an embodiment, a method of processing a substrate is provided. The method includes positioning a substrate in a processing volume of a processing chamber and depositing a diamond-like carbon (DLC) layer on the substrate. After depositing the DLC layer, the film stress is reduced by performing a plasma treatment, wherein the plasma treatment comprises applying a radio frequency (RF) bias power of about 100 W to about 10,000 W.

    Chucking process and system for substrate processing chambers
    14.
    发明授权
    Chucking process and system for substrate processing chambers 有权

    公开(公告)号：US11488811B2

    公开(公告)日：2022-11-01

    申请号：US16803479

    申请日：2020-02-27

    Applicant: Applied Materials, Inc.

    Inventor： Bhaskar Kumar ,  Ganesh Balasubramanian ,  Vivek Bharat Shah ,  Jiheng Zhao

    IPC: H01J37/32 ,  C23C16/50 ,  C23C16/458 ,  C23C16/52

    Abstract: The present disclosure relates to methods and systems for chucking in substrate processing chambers. In one implementation, a method of chucking one or more substrates in a substrate processing chamber includes applying a chucking voltage to a pedestal. A substrate is disposed on a support surface of the pedestal. The method also includes ramping the chucking voltage from the applied voltage, detecting an impedance shift while ramping the chucking voltage, determining a corresponding chucking voltage at which the impedance shift occurs, and determining a refined chucking voltage based on the impedance shift and the corresponding chucking voltage.

    Aluminum fluoride mitigation by plasma treatment
    15.
    发明授权
    Aluminum fluoride mitigation by plasma treatment 有权

    公开(公告)号：US10688538B2

    公开(公告)日：2020-06-23

    申请号：US15653785

    申请日：2017-07-19

    Applicant: Applied Materials, Inc.

    Inventor： Vivek Bharat Shah ,  Anup Kumar Singh ,  Bhaskar Kumar ,  Ganesh Balasubramanian ,  Bok Hoen Kim

    IPC: C23C16/44 ,  B08B7/00 ,  H01J37/32 ,  C23C16/505 ,  B08B9/08 ,  C23C16/50

    Abstract: Implementations described herein generally relate to methods and apparatus for in-situ removal of unwanted deposition buildup from one or more interior surfaces of a semiconductor substrate-processing chamber. In one implementation, the method comprises forming a reactive fluorine species from a fluorine-containing cleaning gas mixture. The method further comprises delivering the reactive fluorine species into a processing volume of a substrate-processing chamber. The processing volume includes one or more aluminum-containing interior surfaces having unwanted deposits formed thereon. The method further comprises permitting the reactive fluorine species to react with the unwanted deposits and aluminum-containing interior surfaces of the substrate-processing chamber to form aluminum fluoride. The method further comprises exposing nitrogen-containing cleaning gas mixture to in-situ plasma to form reactive nitrogen species in the processing volume. The method further comprises permitting the reactive nitrogen species to react with the ammonium fluoride to convert the aluminum fluoride to aluminum nitride.

    SELECTIVE SEALANT REMOVAL
    16.
    发明申请
    SELECTIVE SEALANT REMOVAL 审中-公开
    选择性密封拆卸

    公开(公告)号：US20160172238A1

    公开(公告)日：2016-06-16

    申请号：US14569301

    申请日：2014-12-12

    Applicant: Applied Materials, Inc.

    Inventor： Bhaskar Kumar ,  Deenesh Padhi ,  Alexandros T. Demos ,  Tapash Chakraborty ,  Geetika Bajaj ,  Robert Jan Visser

    IPC: H01L21/768

    CPC classification number: H01L21/76831

    Abstract: A method of forming features in a low-k dielectric layer is described. A via, trench or a dual damascene structure may be present in the low-k dielectric layer prior to depositing a conformal hermetic layer. The conformal hermetic layer is configured to keep water and contaminants out. Some of the same conformal hermetic layer may deposit on the underlying copper. The portion of the conformal hermetic layer on the underlying copper is preferentially removed but the beneficial portion on the low-k dielectric layer remains. The selective removal of the conformal hermetic layer may be accomplished using a dry etch or a wet etch using a weak organic acid.

    Abstract translation: 描述了在低k电介质层中形成特征的方法。 在沉积保形密封层之前，可以在低k电介质层中存在通孔，沟槽或双镶嵌结构。 保形密封层被配置成保持水和污染物排出。 一些相同的保形密封层可能沉积在下面的铜上。 优先除去底层铜上的共形密封层的部分，但是在低k电介质层上的有益部分保留。 选择性去除保形密封层可以使用干蚀刻或使用弱有机酸的湿蚀刻来实现。

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