公开(公告)号：US20140176250A1

公开(公告)日：2014-06-26

申请号：US13721885

申请日：2012-12-20

申请人： Axel Thomsen ,  Pavel Konecny ,  Xiaodong Wang

发明人： Axel Thomsen ,  Pavel Konecny ,  Xiaodong Wang

IPC分类号： H03K3/011

CPC分类号： H03K3/0231

摘要： In an embodiment, a method includes: during a first portion of a cycle of a clock signal generated by an oscillator, pre-charging a first capacitor of a first switched capacitor stage until a first comparator determines that a first node voltage of the first switched capacitor stage is greater than a first reference voltage at a first reference voltage node; applying a second reference voltage to the first reference voltage node; and responsive to a first edge of the clock signal, charging the first capacitor until the first comparator determines that the first node voltage is greater than the second reference voltage at the first reference voltage node.

摘要翻译： 在一个实施例中，一种方法包括：在由振荡器产生的时钟信号的周期的第一部分期间，对第一开关电容器级的第一电容器进行预充电，直到第一比较器确定第一开关的第一节点电压 电容器级大于第一参考电压节点处的第一参考电压; 将第二参考电压施加到所述第一参考电压节点; 并且响应于所述时钟信号的第一边沿，对所述第一电容器充电直到所述第一比较器确定所述第一节点电压大于所述第一参考电压节点处的所述第二参考电压。

公开(公告)号：US08203370B2

公开(公告)日：2012-06-19

申请号：US12494621

申请日：2009-06-30

申请人： Shouli Yan ,  Zhiwei Dong ,  Axel Thomsen

发明人： Shouli Yan ,  Zhiwei Dong ,  Axel Thomsen

IPC分类号： H03K3/00

CPC分类号： H03K3/3565 ,  H03K5/088

摘要： A Schmitt trigger comprises first and second circuitry. The first circuitry receives an input voltage and provides an output voltage at either a logical “low” or a logical “high” voltage level responsive to the input voltage and a first bias voltage. The second circuitry connects to the first circuitry to generate a second bias current for generating the output voltage. The second bias current is larger than the first bias current. The Schmitt trigger operates in a low power mode of operation using only the first bias voltage to maintain the logical “low” voltage level or the logical “high” voltage level at a substantially constant level. In a high power mode of operation the Schmitt trigger uses the second bias voltage during transition periods between the logical “low” voltage level and the logical “high” voltage level.

摘要翻译： 施密特触发器包括第一和第二电路。 第一电路接收输入电压并且响应于输入电压和第一偏置电压在逻辑“低”或逻辑“高”电压电平提供输出电压。 第二电路连接到第一电路以产生用于产生输出电压的第二偏置电流。 第二偏置电流大于第一偏置电流。 施密特触发器仅在第一偏置电压下工作在低功耗工作模式，以将逻辑“低”电压电平或逻辑“高”电压电平维持在基本恒定的水平。 在高功率工作模式下，施密特触发器在逻辑“低”电压电平和逻辑“高”电压电平之间的过渡期间使用第二偏置电压。

公开(公告)号：US07834706B2

公开(公告)日：2010-11-16

申请号：US11571077

申请日：2005-06-28

申请人： Doug Frey ,  Axel Thomsen ,  Ligang Zhang

发明人： Doug Frey ,  Axel Thomsen ,  Ligang Zhang

IPC分类号： H03L7/00

CPC分类号： H03L7/0891 ,  H03L7/1976

摘要： A noise cancellation signal is generated for a fractional-N phase-locked loop (200). A divide value is provided to a first delta sigma modulator circuit (203), which generates a divide control signal to control a divide value of a feedback divider (208) in the phase-locked loop. An error term (e) is generated that is indicative of a difference between the generated divide control signal and the divide value supplied to the first delta sigma modulator circuit. The error term is integrated in an integrator (320) to generate an integrated error term (x), where xk+1=xk+ek; and a phase error correction circuit (209) utilizes the error term ek and the integrated error term xk to generate the phase error cancellation signal.

摘要翻译： 对于分数N锁相环（200）产生噪声消除信号。 分频值被提供给第一ΔΣ调制器电路（203），其产生除法控制信号以控制锁相环中的反馈分频器（208）的除法值。 生成指示所生成的除法控制信号和提供给第一ΔΣ调制器电路的除法值之间的差异的误差项（e）。 误差项集成在积分器（320）中以产生积分误差项（x），其中xk + 1 = xk + ek; 并且相位误差校正电路（209）利用误差项ek和积分误差项xk来产生相位误差消除信号。

公开(公告)号：US07295077B2

公开(公告)日：2007-11-13

申请号：US11270954

申请日：2005-11-10

申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein ,  Michael Petrowski, III

发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein ,  Michael Petrowski, III

IPC分类号： H03B21/00

CPC分类号： H03L7/23 ,  H03L7/0898 ,  H03L7/197 ,  H03L7/1976

摘要： A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.

摘要翻译： 锁相环（PLL）电路包括用于接收定时参考信号的输入端，耦合以接收定时参考信号的相位检测器电路，根据相位检测器电路的输出控制的可控振荡器电路，以及反馈分配器 电路具有耦合到相位检测器的输出端和耦合到可控振荡器电路的输入端。 锁相环电路根据频率选择机构耦合到输出具有任意频率关系的多个输出信号中的一个，所述频率选择机构包括一个或多个输入端，用于控制所述频率选择机构的分频比 反馈分频电路。 频率选择机构选择多个存储值中的一个。 选择的存储值至少部分地控制反馈分频器电路的分频比，从而提供能够在彼此具有任意关系的输出频率之间进行选择的引脚可编程器件。

公开(公告)号：US07236024B2

公开(公告)日：2007-06-26

申请号：US11239943

申请日：2005-09-30

申请人： Yunteng Huang ,  Ligang Zhang ,  Axel Thomsen

发明人： Yunteng Huang ,  Ligang Zhang ,  Axel Thomsen

IPC分类号： H03L7/06

CPC分类号： G06F7/68 ,  H03L7/183 ,  H03L7/23

摘要： A PLL function may be implemented as a dual-loop structure having a first PLL circuit which generates an intermediate signal from the reference signal, and a second PLL circuit which generates an output signal from the intermediate signal. The intermediate signal frequency is preferably chosen at a value in which potential interference signals do not have much energy. The first loop preferably has low bandwidth to provide good input jitter attenuation, while second loop preferably has higher bandwidth to reduce phase noise of the output signal. The circuit preferably provides for a choice of several different intermediate frequencies to allow use where different intermediate frequencies may exist in each system. Moreover, in a system having two such dual-loop PLL circuits, each can be configured with a different intermediate frequency, so that interference from one to the other is reduced.

摘要翻译： PLL功能可以实现为具有从参考信号产生中间信号的第一PLL电路的双回路结构，以及从中间信号产生输出信号的第二PLL电路。 中间信号频率优选地被选择为其中潜在的干扰信号没有太多能量的值。 第一环路优选具有低带宽以提供良好的输入抖动衰减，而第二环路优选地具有较高带宽以减少输出信号的相位噪声。 该电路优选地提供几种不同中频的选择，以允许在每个系统中可能存在不同中频的应用。 此外，在具有两个这样的双回路PLL电路的系统中，每个都可以配置有不同的中频，从而减少了从一个到另一个的干扰。

公开(公告)号：US20070139088A1

公开(公告)日：2007-06-21

申请号：US11680026

申请日：2007-02-28

申请人： Akhil Garlapati ,  Lizhong Sun ,  Douglas Pastorello ,  Richard Juhn ,  Axel Thomsen

发明人： Akhil Garlapati ,  Lizhong Sun ,  Douglas Pastorello ,  Richard Juhn ,  Axel Thomsen

IPC分类号： H03K23/00

CPC分类号： H03K23/66 ,  H03K21/10 ,  H03L7/0805 ,  H03L7/087 ,  H03L7/091 ,  H03L7/093 ,  H03L7/193 ,  H03L7/1974 ,  H03L7/1976

摘要： In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first plurality of signals having a common frequency, a first pulse width, and different phases. The first plurality of signals is based, at least in part, on at least one signal having a second pulse width. The first pulse width is selected from a plurality of pulse widths based, at least in part, on the divide ratio. The method includes sequentially selecting individual pulses of the first plurality of signals as an output signal of a select circuit to generate an output signal having a frequency lower than the first frequency.

摘要翻译： 在本发明的至少一个实施例中，一种用于将具有第一频率的第一信号除以分频比以产生较低频率信号的方法包括产生具有共同频率，第一脉冲宽度和不同相位的第一多个信号 。 第一组多个信号至少部分地基于具有第二脉冲宽度的至少一个信号。 至少部分地基于分频比，从多个脉冲宽度中选择第一脉冲宽度。 该方法包括顺序选择第一多个信号中的各个脉冲作为选择电路的输出信号，以产生具有低于第一频率的频率的输出信号。

公开(公告)号：US07187241B2

公开(公告)日：2007-03-06

申请号：US10675543

申请日：2003-09-30

申请人： Jerrell Hein ,  Axel Thomsen

发明人： Jerrell Hein ,  Axel Thomsen

IPC分类号： H03L7/00

CPC分类号： H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

摘要： A clock device having a resonating device such as a crystal of SAW supplying a controllable oscillator such as a digitally controlled oscillator is calibrated by supplying a calibration clock. A phase-locked loop is utilized to generate one or more correction factors causing the PLL to lock to the calibration clock. The one or more correction factors are then stored in non-volatile memory.

摘要翻译： 通过提供校准时钟来校准具有诸如数字控制振荡器等可控振荡器的SAW的晶体谐振装置的时钟装置。 利用锁相环产生一个或多个校正因子，使PLL锁定到校准时钟。 然后将一个或多个校正因子存储在非易失性存储器中。

公开(公告)号：US06614285B2

公开(公告)日：2003-09-02

申请号：US09054521

申请日：1998-04-03

申请人： Wai Laing Lee ,  Dan Kasha ,  Axel Thomsen

发明人： Wai Laing Lee ,  Dan Kasha ,  Axel Thomsen

IPC分类号： G06G7186

CPC分类号： G06G7/1865

摘要： Power available to an integrator circuit is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing in a device is expected and relatively low power is provided during another phase. In one implementation, increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in a particular interval. The techniques are particularly useful when applied to clocked integrator circuits.

摘要翻译： 对集成电路可用的功率进行控制，使得在一个操作阶段期间提供相对较高的功率，例如在期望设备中回转的间隔期间，并且在另一阶段期间提供相对较低的功率。 在一个实施方式中，当功率需求预期为高时，无论在特定间隔中是否实际需要高功率，通过切换并联电流镜来提供功率增加。 当应用于时钟积分器电路时，这些技术特别有用。

公开(公告)号：US06445791B1

公开(公告)日：2002-09-03

申请号：US09370404

申请日：1999-08-09

申请人： Robert Thomas Grisamore ,  Kartika Putra Prihadi ,  Eric Swanson ,  Karl Nordling ,  Axel Thomsen

发明人： Robert Thomas Grisamore ,  Kartika Putra Prihadi ,  Eric Swanson ,  Karl Nordling ,  Axel Thomsen

IPC分类号： H04M100

CPC分类号： H04L25/085 ,  H04L25/0266

摘要： An interface for coupling a modem port with a transmission line includes a hybrid converter having a variable gain amplifier coupling a transmit path of a first differential polarity and a received path of a second differential polarity.

摘要翻译： 用于将调制解调器端口与传输线耦合的接口包括具有耦合第一差分极性的发送路径和第二差分极性的接收路径的可变增益放大器的混合转换器。

公开(公告)号：US06369745B1

公开(公告)日：2002-04-09

申请号：US09054542

申请日：1998-04-03

申请人： Wai Laing Lee ,  Dan Kasha ,  Axel Thomsen

发明人： Wai Laing Lee ,  Dan Kasha ,  Axel Thomsen

IPC分类号： H03M150

CPC分类号： H03M3/32 ,  H03M3/374 ,  H03M3/43 ,  H03M3/448 ,  H03M3/452

摘要： Power available to a delta sigma modulator is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing in a device is expected and relatively low power is provided during another phase. In one implementation, increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in a particular interval. A large step size is selected to reduce power corruption and feedback coefficients are optimized for low power by running at a higher oversampling rate than required by signal to quantization noise requirements.

摘要翻译： 控制对ΔΣ调制器的可用功率，使得在一个操作阶段期间提供相对较高的功率，例如在期望设备中回转的间隔期间，并且在另一阶段期间提供相对较低的功率。 在一个实施方式中，当功率需求预期为高时，无论在特定间隔中是否实际需要高功率，通过切换并联电流镜来提供功率增加。 选择大的步长以减少功率损耗，并且通过以比信号对量化噪声要求所要求的更高的过采样速率运行来为低功率优化反馈系数。