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Patent Agency Ranking
11.发明申请公开(公告)号：US20200380931A1
公开(公告)日：2020-12-03
申请号：US16469530
申请日：2018-09-10
Inventor： Zhangmeng Wang , Yimin Chen , Xianjie Shao
IPC: G09G3/36
Abstract: A gate driving unit, a method for driving the same, a gate driving circuitry and a display module are provided. The gate driving unit includes: a shift register circuit configured to delay a phase of an input signal inputted by a signal input end under control of a first clock signal input end and a second clock signal input end to obtain a carry signal, and output the carry signal through a carry end; and a pulse width regulation circuit configured to regulate a pulse width of the carry signal under control of the enable end to obtain a gate drive signal, and output the gate drive signal through a gate drive signal output end.
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12.发明授权公开(公告)号：US11120762B2
公开(公告)日：2021-09-14
申请号：US16469530
申请日：2018-09-10
Inventor： Zhangmeng Wang , Yimin Chen , Xianjie Shao
Abstract: A gate driving unit, a method for driving the same, a gate driving circuitry and a display module are provided. The gate driving unit includes: a shift register circuit configured to delay a phase of an input signal inputted by a signal input end under control of a first clock signal input end and a second clock signal input end to obtain a carry signal, and output the carry signal through a carry end; and a pulse width regulation circuit configured to regulate a pulse width of the carry signal under control of the enable end to obtain a gate drive signal, and output the gate drive signal through a gate drive signal output end.
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13.发明授权公开(公告)号：US10573262B2
公开(公告)日：2020-02-25
申请号：US15934060
申请日：2018-03-23
Inventor： Yimin Chen , Xianjie Shao , Xiujuan Wang , Zhangmeng Wang
IPC: G09G3/36
Abstract: The disclosure discloses a data voltage storage circuit, a method for driving the same, a liquid crystal display, and a display device, and the data voltage storage circuit includes a voltage input subcircuit, a storage control subcircuit, and an output control subcircuit; and the storage control subcircuit stores a data signal input to the first node, so that the data signal can be stored for a long period of time. The three subcircuits above cooperate with each other so that a signal output end can be provided with a signal of a second reference voltage signal end or a common voltage signal end using the simple structure to thereby lower the difficulty of a fabrication process thereof, narrow a space to be occupied by the circuit, and improve a pixel aperture ratio.
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14.发明申请公开(公告)号：US20190206914A1
公开(公告)日：2019-07-04
申请号：US16030981
申请日：2018-07-10
Inventor： Yimin Chen , Xianjie Shao
IPC: H01L27/146 , G06K9/00
CPC classification number: H01L27/14612 , G06K9/0004 , G06K9/00087 , H01L27/14634 , H01L27/14636 , H01L27/1469
Abstract: Embodiments of the present disclosure provide a display panel, a method of manufacturing the display panel, a fingerprint identification device, and a method of identifying a fingerprint. The display panel includes first and second substrates. The first substrate is formed with switch transistors arranged in an array, and photosensitive elements arranged in an array and connected with the switch transistors. The second substrate is formed with conductive contact members, the contact members each have an end adjacent to the first substrate, and the end of each of the contact members is spaced from the first substrate so that when the second substrate is deformed by a force, the end of at least one of the contact members electrically contacts the first substrate so that at least one of the switch transistors in a position corresponding to the at least one of the contact members is turned on.
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公开(公告)号：US20190130856A1
公开(公告)日：2019-05-02
申请号：US15953391
申请日：2018-04-13
Inventor： Yimin Chen , Xianjie Shao , Li Sun
Abstract: A shift register unit, a gate driving circuit, a display apparatus and a driving method are provided. The shift register unit comprises a data register circuit and a data output circuit both electrically connected to a first node. The data register circuit is configured to register an input signal from an input terminal at the first node; and the data output circuit is configured to output the input signal registered at the first node to an output terminal in response to a first clock signal from a first clock signal terminal. The shift register unit can realize a self-resetting function. The first node can be reset under control of the first clock signal and a second clock signal from a second clock signal terminal.
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