公开(公告)号：US20100064121A1

公开(公告)日：2010-03-11

申请号：US12208683

申请日：2008-09-11

申请人： Gregory W. Alexander ,  Brian D. Barrick ,  Lee E. Eisen ,  John W. Ward, III

发明人： Gregory W. Alexander ,  Brian D. Barrick ,  Lee E. Eisen ,  John W. Ward, III

IPC分类号： G06F9/30

CPC分类号： G06F9/3838

摘要： A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are employed as follows: a Load-Store Unit (LSU) dependency matrix is written with the plurality of LSU dependencies and a non-LSU dependency matrix is written with the plurality of non-LSU dependencies; an LSU issue valid (LSU IV) indicator is set as valid to issue; an LSU portion of the dual-issue instruction is issued once the plurality of LSU dependencies of the dual issue instruction are satisfied; a non-LSU issue valid (non-LSU IV) indicator is set as valid to issue; and a non-LSU portion of the dual-issue instruction is issued once the plurality of non-LSU dependencies of the dual issue instruction are satisfied. The LSU dependency matrix and the non-LSU dependency matrix can then be notified that one or more instructions dependent upon the dual-issue instruction may now issue.

摘要翻译： 解码双发指令以确定双发指令的LSU部分所需的多个LSU依赖性以及双发指令的非LSU部分所需的多个非LSU依赖性。 在由微处理器发出双发指令的情况下，双依赖矩阵采用如下方式：加载存储单元（LSU）依赖矩阵用多个LSU依赖性写入，非LSU依赖矩阵用 多个非LSU依赖关系; LSU问题有效（LSU IV）指标设置为有效发行; 一旦满足双重发出指令的多个LSU依赖性，就发出双发指令的LSU部分; 非LSU问题有效（非LSU IV）指标被设置为有效发行; 一旦满足双重发出指令的多个非LSU依赖关系，就发出双发指令的非LSU部分。 然后可以通知LSU依赖矩阵和非LSU依赖矩阵，使得依赖于双重发出指令的一个或多个指令现在可以被发布。

公开(公告)号：US5805475A

公开(公告)日：1998-09-08

申请号：US816067

申请日：1997-03-11

申请人： Michael Putrino ,  Lee E. Eisen

发明人： Michael Putrino ,  Lee E. Eisen

IPC分类号： G06F7/57 ,  G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F7/00 ,  G06F7/38

CPC分类号： G06F9/30043 ,  G06F7/483 ,  G06F9/30014 ,  G06F9/30025 ,  G06F2207/382 ,  G06F7/49905

摘要： A floating point numbers load-store unit includes a translator for converting between the single-precision and double-precision representations, and Special-Case logic for providing Special-Case signals when a store is being performed on zero, infinity, or NaN. A store-float-double instruction is executed by concatenating a suffix to the mantissa in the single-precision floating-point register and replacing the high-order bit of the exponent with a prefix selected as a function of the high-order bit, wherein the resulting mantissa and exponent form a double-precision floating-point number that is then stored to memory. A load-float-double instruction is executed by dropping the suffix from the mantissa of the double-precision floating-point number in memory, and replacing the prefix with the high-order bit, wherein the resulting mantissa and exponent form a single-precision floating-point number that is then loaded into the single-precision floating-point register.

摘要翻译： 浮点数加载存储单元包括用于在单精度和双精度表示之间进行转换的转换器，以及当在零，无穷大或NaN上执行存储时提供特殊情况信号的特殊情况逻辑。 通过将后缀连接到单精度浮点寄存器中的尾数来执行store-float-double指令，并且以由高位位选择的前缀替换指数的高位，其中 所得到的尾数和指数形成双精度浮点数，然后将其存储到存储器中。 通过从存储器中的双精度浮点数的尾数丢弃后缀，并用高位替换前缀，执行load-float-double指令，其中所得到的尾数和指数形成单精度 浮点数然后加载到单精度浮点寄存器中。