Abstract:
Presented is a system and method for testing a digital video distribution environment. A digital video signal generator transmits a reference video bit stream to a distribution path. A digital video signal analyzer receives a test video bit stream from the distribution path. The digital video signal analyzer generates a diagnostic video bit stream as a function of the reference video bit stream and the test video bit stream.
Abstract:
When switching sources, resolutions or refresh rates in a video distribution network, switching times are reduced by maintaining video lock and security authentication between a video switcher and a video sink. The scaler maintains video lock and security authentication by continuing to generate video timing data during switching events. The scaler also facilitates an aesthetically pleasing transition by generating image content data prior to and after the switching event.
Abstract:
Presented is a system and method for testing a digital video distribution environment. A digital video signal generator transmits a reference video bit stream to a distribution path. A digital video signal analyzer receives a test video bit stream from the distribution path. The digital video signal analyzer generates a diagnostic video bit stream as a function of the reference video bit stream and the test video bit stream.
Abstract:
When switching sources, resolutions or refresh rates in a video distribution network, switching times are reduced by maintaining video lock and security authentication between a video switcher and a video sink. The scaler maintains video lock and security authentication by continuing to generate video timing data during switching events. The scaler also facilitates an aesthetically pleasing transition by generating image content data prior to and after the switching event.
Abstract:
An input card of video switcher includes a detection block for detecting errors in the timing signals of a digital video signal within a range. For timing signals with errors that fall within the range, the input card implements a correction block to correct the signals to an expected resolution. For timing signals with errors that fall out of the range, the input card does implement the correction block and passes the raw timing signal through.