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86 条记录 (耗时 0.024 秒)

    POLARITY DEPENDENT SWITCH FOR RESISTIVE SENSE MEMORY
    11.
    发明申请
    POLARITY DEPENDENT SWITCH FOR RESISTIVE SENSE MEMORY 有权
    极性依赖开关电感式记忆

    公开(公告)号：US20110032748A1

    公开(公告)日：2011-02-10

    申请号：US12903301

    申请日：2010-10-13

    申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

    发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

    IPC分类号： G11C11/00 ,  H01L29/78

    CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

    摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.

    摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。

    Polarity dependent switch for resistive sense memory
    12.
    发明授权
    Polarity dependent switch for resistive sense memory 有权
    用于电阻式读出存储器的极性依赖开关

    公开(公告)号：US08508980B2

    公开(公告)日：2013-08-13

    申请号：US13278334

    申请日：2011-10-21

    申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

    发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

    IPC分类号： H01L29/78 ,  H01L45/00 ,  G11C11/00

    CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

    摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.

    摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。

    MAGNETIC MEMORY WITH MAGNETIC TUNNEL JUNCTION CELL SETS
    13.
    发明申请
    MAGNETIC MEMORY WITH MAGNETIC TUNNEL JUNCTION CELL SETS 有权
    磁性记忆与磁性隧道连接电池组

    公开(公告)号：US20100124106A1

    公开(公告)日：2010-05-20

    申请号：US12272896

    申请日：2008-11-18

    申请人： Young Pil Kim ,  Chulmin Jung ,  Hyung-Kew Lee ,  Insik Jin ,  Michael Xuefei Tang

    发明人： Young Pil Kim ,  Chulmin Jung ,  Hyung-Kew Lee ,  Insik Jin ,  Michael Xuefei Tang

    IPC分类号： G11C11/14 ,  G11C7/00 ,  G11C11/409

    CPC分类号： G11C11/1673 ,  G11C11/161

    摘要： A memory apparatus having at least one memory cell set comprising a first spin torque memory cell electrically connected in series to a second spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The memory cell set itself is configured to switch between a high resistance state and a low resistance state. The memory apparatus also has at least one reference cell set comprising a third spin torque memory cell electrically connected in anti-series to a fourth spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The reference cell set itself has a reference resistance that is a midpoint of the high resistance state and the low resistance state of the memory cell set.

    摘要翻译： 一种存储装置，具有至少一个存储单元组，其包括与第二自旋转矩存储单元串联电连接的第一自旋转矩存储单元，每个自旋转矩存储单元被配置为在高电阻状态和低电阻状态之间切换。 存储单元组自身被配置为在高电阻状态和低电阻状态之间切换。 存储装置还具有至少一个参考单元组，其包括与第四自旋转矩存储单元反串联电连接的第三自旋转矩存储单元，每个自旋转矩存储单元被配置为在高电阻状态和低电阻之间切换 州。 参考单元组本身具有作为存储单元组的高电阻状态和低电阻状态的中点的参考电阻。

    Vertical transistor with hardening implatation
    19.
    发明授权
    Vertical transistor with hardening implatation 有权
    垂直晶体管与硬化插入

    公开(公告)号：US08617952B2

    公开(公告)日：2013-12-31

    申请号：US12891966

    申请日：2010-09-28

    申请人： Young Pil Kim ,  Hyung-Kew Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  Maroun Georges Khoury ,  Dadi Setiadi

    发明人： Young Pil Kim ,  Hyung-Kew Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  Maroun Georges Khoury ,  Dadi Setiadi

    IPC分类号： H01L21/336

    CPC分类号： H01L45/1233 ,  H01L27/228 ,  H01L27/2454 ,  H01L45/1206

    摘要： A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.

    摘要翻译： 一种方法包括提供具有从半导体晶片正交延伸的多个柱结构的半导体晶片。 每个柱结构形成具有与顶表面正交的顶表面和侧表面的垂直柱状晶体管。 然后将硬化物质注入垂直柱晶体管顶表面。 然后，垂直柱状晶体管侧面被氧化，形成侧面氧化层。 去除侧面氧化物层以形成具有圆形侧表面的垂直柱状晶体管。