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11.发明授权Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments 失效具有用于传送操作数段的多个操作数总线的超标量微处理器的混合整数/浮点处理器核公开(公告)号：US5574928A
公开(公告)日：1996-11-12
申请号：US233563
申请日：1994-04-26
Applicant: Scott A. White , Michael D. Goddard , William M. Johnson
Inventor： Scott A. White , Michael D. Goddard , William M. Johnson
CPC classification number: G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30094 , G06F9/30149 , G06F9/3802 , G06F9/3806 , G06F9/3814 , G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3885
Abstract: A processor core for supporting the concurrent execution of mixed integer and floating point operations includes integer functional units (110) utilizing 32-bit operand data and a floating point functional unit (22) utilizing up to 82-bit operand data. Eight operand busses (30, 31) connect to the functional units to furnish operand data, and five result busses (32) are connected to the functional units to return results. The width of the operand busses is 41 bits, which is sufficient to communicate either integer or floating point data. This is done using an instruction decoder (18) to apportion a floating point operation which operates on 82-bit floating point operand data into multiple suboperations each associated with a 41-bit suboperand. The operand busses and result busses have an expanded data-handling dimension from the standard integer data width of 32 bits to 41 bits for handling the floating point operands. The floating point functional unit recombines the suboperand data into 82-bits for execution of the floating point operation, and partitions the 82-bit result for output to the result busses. In addition, the excess capacity of the result busses during integer transfers is used to communicate integer flags.
Abstract translation: 用于支持并行执行混合整数和浮点运算的处理器核心包括利用32位操作数数据的整数功能单元（110）和利用高达82位操作数数据的浮点功能单元（22）。 八个操作数总线（30,31）连接到功能单元以提供操作数据，并且五个结果总线（32）连接到功能单元以返回结果。 操作数总线的宽度为41位，足以传送整数或浮点数据。 这是使用指令解码器（18）来完成的，以将对82位浮点运算数据进行操作的浮点运算分配成与41位子波段相关的多个子波形。 操作数总线和结果总线具有从32位的标准整数数据宽度到41位的扩展数据处理维度，用于处理浮点操作数。 浮点功能单元将小波段数据重新组合为82位，用于执行浮点运算，并将82位结果分割为结果总线。 此外，整数传输期间结果总线的剩余容量用于通信整数标志。
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公开(公告)号：US5696955A
公开(公告)日：1997-12-09
申请号：US252303
申请日：1994-06-01
Applicant: Michael D. Goddard , Scott A. White
Inventor： Michael D. Goddard , Scott A. White
CPC classification number: G06F7/785 , G06F9/30032 , G06F9/3004 , G06F9/30112 , G06F9/30134 , G06F9/3806 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
Abstract: In a processor (110) that performs multiple instructions in a single cycle, predicts outcomes of branch conditions and speculatively executes instructions based on the branch predictions, a method and apparatus for operating a data stack utilize a remap array (674) to support a stack exchange capability. The remap array is used to correlate a stack pointer (672) to data elements (700) within the stack. A lookahead stack pointer (502) and remap array (504) are updated to preserve the processor's state of operation while speculative instructions are executed.
Abstract translation: 在单个周期中执行多个指令的处理器（110）中，预测分支条件的结果并基于分支预测推测地执行指令，用于操作数据堆栈的方法和装置利用重映射阵列（674）来支持堆栈 交换能力。 重映射数组用于将堆栈指针（672）与堆栈内的数据元素（700）相关联。 更新前瞻堆栈指针（502）和重新映射数组（504）以在执行推测性指令时保持处理器的操作状态。
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公开(公告)号：US5764938A
公开(公告)日：1998-06-09
申请号：US797434
申请日：1997-02-10
Applicant: Scott A. White , Michael D. Goddard
Inventor： Scott A. White , Michael D. Goddard
CPC classification number: G06F9/30032 , G06F9/3812 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
Abstract: Operations of a pipeline processor (110) are resynchronized under designated conditions. The processor updates a fetch program counter (210) and, as directed by the counter, fetches instructions from a memory (114). The processor concurrently dispatches, in the fetched order, multiple instructions to designated functional units (170, 171, 172, 173, 174 and 175). Dispatched instructions are queued in functional unit reservation stations. Result entries corresponding to the queued instructions are allocated in a reorder buffer 126 queue in their order of dispatch. Instructions are executed out of their fetched order and results are entered in the allocated result entries when execution is complete. Allocated result entries at the head of the reorder buffer queue are retired and an instruction pointer (620) is updated. The processor is resynchronized when it detects a resynchronization condition and acknowledges the resynchronization condition in the allocated result entry corresponding to the instruction that detected the condition. When the reorder buffer entry holding the resynchronization acknowledgement is retired, the processor flushes the reorder buffer and the reservation stations of the functional units and redirects the fetch program counter to the instruction addressed by the instruction pointer.
Abstract translation: 流水线处理器（110）的操作在指定条件下重新同步。 处理器更新获取程序计数器（210），并且如由计数器指示的，从存储器（114）中取出指令。 处理器以获取的顺序并发地分配指定的功能单元（170,171,172,173,174和175）的多个指令。 分派的指令在功能单元保留站中排队。 与排队指令相对应的结果条目按其分配顺序分配在重新排序缓冲器126队列中。 指令从其获取的顺序执行，并且执行完成后，结果将输入到分配的结果条目中。 在排序缓冲器队列的头部处的分配结果条目被退休，并且更新指令指针（620）。 当处理器检测到重新同步状态并确认与检测到条件的指令相对应的分配结果条目中的重新同步状态时，处理器被重新同步。 当保持重新同步确认的重新排序缓冲器条目被停止时，处理器刷新重排序缓冲器和功能单元的保留站，并将获取程序计数器重定向到由指令指针寻址的指令。
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公开(公告)号：US5649225A
公开(公告)日：1997-07-15
申请号：US252308
申请日：1994-06-01
Applicant: Scott A. White , Michael D. Goddard
Inventor： Scott A. White , Michael D. Goddard
CPC classification number: G06F9/30032 , G06F9/3812 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
Abstract: Operations of a pipeline processor (110) are resynchronized under designated conditions. The processor updates a fetch program counter (210) and, as directed by the counter, fetches instructions from a memory (114). The processor concurrently dispatches, in the fetched order, multiple instructions to designated functional units (170, 171, 172, 173, 174 and 175). Dispatched instructions are queued in functional unit reservation stations. Result entries corresponding to the queued instructions are allocated in a reorder buffer 126 queue in their order of dispatch. Instructions are executed out of their fetched order and results are entered in the allocated result entries when execution is complete. Allocated result entries at the head of the reorder buffer queue are retired and an instruction pointer (620) is updated. The processor is resynchronized when it detects a resynchronization condition and acknowledges the resynchronization condition in the allocated result entry corresponding to the instruction that detected the condition. When the reorder buffer entry holding the resynchronization acknowledgement is retired, the processor flushes the reorder buffer and the reservation stations of the functional units and redirects the fetch program counter to the instruction addressed by the instruction pointer.
Abstract translation: 流水线处理器（110）的操作在指定条件下重新同步。 处理器更新获取程序计数器（210），并且如由计数器指示的，从存储器（114）中取出指令。 处理器以获取的顺序并发地分配指定的功能单元（170,171,172,173,174和175）的多个指令。 分派的指令在功能单元保留站中排队。 与排队指令相对应的结果条目按其分配顺序分配在重新排序缓冲器126队列中。 指令从其获取的顺序执行，并且执行完成后，结果将输入到分配的结果条目中。 在排序缓冲器队列的头部处的分配结果条目被退休，并且更新指令指针（620）。 当处理器检测到重新同步状态并确认与检测到条件的指令相对应的分配结果条目中的重新同步状态时，处理器被重新同步。 当保持重新同步确认的重新排序缓冲器条目被停止时，处理器刷新重排序缓冲器和功能单元的保留站，并将获取程序计数器重定向到由指令指针寻址的指令。
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公开(公告)号：US07350119B1
公开(公告)日：2008-03-25
申请号：US10859284
申请日：2004-06-02
Applicant: Gerald D. Zuraski, Jr. , Scott A. White
Inventor： Gerald D. Zuraski, Jr. , Scott A. White
CPC classification number: G11C29/44 , G06F12/0802 , G11C29/4401 , G11C29/802 , G11C2029/0401
Abstract: A hierarchical encoding format for coding repairs to devices within a computing system. A device, such as a cache memory, is logically partitioned into a plurality of sub-portions. Various portions of the sub-portions are identifiable as different levels of hierarchy of the device. A first sub-portion may corresponds to a particular cache, a second sub-portion may correspond to a particular way of the cache, and so on. The encoding format comprises a series of bits with a first portion corresponding to a first level of the hierarchy, and a second portion of the bits corresponds to a second level of the hierarchy. Each of the first and second portions of bits are preceded by a different valued bit which serves to identify the hierarchy to which the following bits correspond. A sequence of repairs are encoded as string of bits. The bit which follows a complete repair encoding indicates whether a repair to the currently identified cache is indicated or whether a new cache is targeted by the following repair. Therefore, certain repairs may be encoded without respecifying the entire hierarchy.
Abstract translation: 用于对维修计算系统内的设备进行编码的分层编码格式。 诸如高速缓冲存储器的设备被逻辑地分割成多个子部分。 子部分的各个部分可被识别为设备的不同层级。 第一子部分可以对应于特定高速缓存，第二子部分可以对应于高速缓存的特定方式，等等。 编码格式包括一系列位，其中第一部分对应于层级的第一级，并且位的第二部分对应于层级的第二级。 位的第一和第二部分中的每一个前面都有一个不同的值，用于识别跟随位对应的层级。 维修序列被编码为位串。 遵循完整修复编码的位指示是否指示对当前标识的高速缓存的修复，或者是否通过以下修复来定位新的高速缓存。 因此，可以编码某些修复，而不需要重新整理层次结构。
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16.发明授权Resolving dependencies among concurrently dispatched instructions in a superscalar microprocessor 失效在超标量微处理器中解析并发调度指令之间的依赖关系
公开(公告)号：US06542986B1
公开(公告)日：2003-04-01
申请号：US09437086
申请日：1999-11-09
Applicant: Scott A. White
Inventor： Scott A. White
IPC: G06F938
CPC classification number: G06F9/382 , G06F9/30152 , G06F9/3816 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
Abstract: A superscalar processor may issue multiple instructions per clock cycle. Included in a superscalar processor may be a reorder buffer which stores information corresponding to concurrently dispatched instructions. Dependencies may exist among the instructions which are concurrently dispatched. To resolve this dependency, when a dependency is detected amongst a group of concurrently dispatched instructions, an indication of the dependency, along with an indication of the position of the dependency, is conveyed to the corresponding reservation station. When the reservation station receives the indication of the dependency, the operand tag associated with the dependency may be replaced with the correct tag. Advantageously, the circuitry needed to resolve the dependency may be moved out of the critical path of the processor; thus, improving the performance of the processor by allowing it to operate at an increased frequency.
Abstract translation: 超标量处理器可以在每个时钟周期发出多个指令。 包含在超标量处理器中可以是重排序缓冲器，其存储与并发分派指令相对应的信息。 在同时发送的指令之间可能存在依赖关系。 为了解决这种依赖性，当在一组并行调度的指令中检测到依赖性时，依赖关系的指示连同依赖关系的位置的指示被传送到相应的保留站。 当保留站接收到依赖关系的指示时，与依赖关联的操作数标签可以被替换为正确的标签。 有利的是，解决依赖性所需的电路可以被移出处理器的关键路径; 因此，通过允许其以增加的频率操作来提高处理器的性能。
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公开(公告)号：US06442707B1
公开(公告)日：2002-08-27
申请号：US09430120
申请日：1999-10-29
Applicant: Kevin J. McGrath , Michael T. Clark , Scott A. White
Inventor： Kevin J. McGrath , Michael T. Clark , Scott A. White
IPC: H02H305
CPC classification number: G06F9/3861 , G06F9/32
Abstract: In a processor a reorder buffer maintains a load/store (LS) fault address register (LSFAR). When the processor's load/store unit reports most LS exceptions, the reorder buffer redirects the microcode unit of the processor to execute a fault handler indicated by an address stored in the LSFAR. The LSFAR may be mapped into the register space of the processor. It may be written by a microcode routine with the address of a specific fault handler at the beginning of a microcode routine or at any time during a microcode routine. As the reorder buffer retires instructions it checks for writes to the LSFAR. If one exists, the reorder buffer loads the result data of that write into the LSFAR. In a preferred embodiment the reorder buffer retires instructions in program order and the LSFAR is not updated speculatively. Also, in a preferred embodiment, when a microcode routine exits, the LSFAR is automatically returned to a default value which indicates a generic fault handling routine.
Abstract translation: 在处理器中，重排序缓冲器维护加载/存储（LS）故障地址寄存器（LSFAR）。 当处理器的加载/存储单元报告大多数LS异常时，重排序缓冲区重定向处理器的微代码单元，以执行由存储在LSFAR中的地址指示的故障处理程序。 LSFAR可以映射到处理器的寄存器空间。 微代码程序可以在微代码程序的开始处或在微代码程序中的任何时间由具有特定故障处理程序的地址的微代码程序写入。 当重新排序缓冲区退出指令时，它会检查对LSFAR的写入。 如果存在，则重新排序缓冲区将该写入的结果数据加载到LSFAR中。 在优选实施例中，重新排序缓冲器以程序顺序退出指令，LSFAR不被推测更新。 此外，在优选实施例中，当微代码例程退出时，LSFAR自动返回到指示通用故障处理例程的默认值。
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18.发明授权Range finding circuit for selecting a consecutive sequence of reorder buffer entries using circular carry lookahead 失效测距电路，用于使用循环进位先行选择连续的重排序缓冲器序列序列
公开(公告)号：US5689693A
公开(公告)日：1997-11-18
申请号：US233568
申请日：1994-04-26
Applicant: Scott A. White
Inventor： Scott A. White
CPC classification number: G06F7/764 , B24B37/042 , G06F7/74 , G06F9/30018
Abstract: A enable circuit (700), employing a "circular carry lookahead" technique to increase its speed performance, is provided for applying two pointers to a circular buffer--an enabling pointer (tail (218)) and a disabling pointer (head (216))--and for generating a multiple-bit enable, ENA (722) in accordance with the pointer values. The pointers designate enable bit boundaries for isolating enable bits of one logic level from enable bits of an opposite logic level. The enable circuit includes several lookahead cells (702, 704, 706 and 708) arranged in an hierarchical array, each of the cells including bits that continue the hierarchical significance. Each cell receives an hierarchical portion of the enabling pointer 218 and the disabling pointer head and a carry. From these pointers, the cell derives a generate, a propagate and the enable bits with a corresponding hierarchical significance. The propagates, generates and carries for all of the lookahead cells are interconnected using a circular propagate carry circuit (710) that provides for asserting a carry to a lookahead cell unless an intervening cell having a nonasserted propagate is interposed in the order of hierarchical significance between the cell and a cell in which enablement is generated.
Abstract translation: 提供了使用“循环进位前瞻”技术来增加其速度性能的使能电路（700），用于将两个指针应用于循环缓冲器 - 使能指针（尾部<3：0>（218））和禁用指针 （头<3：0>（216）） - 并且用于根据指针值产生多位使能ENA（722）。 指针指定使能位边界，用于将一个逻辑电平的使能位与相反逻辑电平的使能位隔离开。 使能电路包括以分层阵列布置的几个前视单元（702,704,706和708），每个单元包括继续层次重要性的位。 每个单元接收使能指针218和禁用指针头<3：0>和进位的分层部分。 从这些指针中，单元格导出生成，传播和具有相应层次重要性的使能位。 传播，产生和携带所有的前瞻性小区是使用环形传播携带电路（710）相互连接的，该环路传播携带电路（710）提供将前进小区的进位断言，除非具有非惰性传播的中间小区按照层次重要性的顺序插入 该单元和其中产生启用的单元。
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公开(公告)号：US4789284A
公开(公告)日：1988-12-06
申请号：US116954
申请日：1987-11-05
Applicant: Scott A. White
Inventor： Scott A. White
CPC classification number: F16B13/066 , E21D21/0053 , E21D21/008
Abstract: The present invention relates to expansison anchors for solid wall installation and is specifically concerned with providing a self cutting expansion anchor which can be installed in one continuous motion by utilizing combined cutting blades and wall gripping members which cut their own undercut portion within a wall bore into which the gripping members are then permanently further expanded in positive locking engagement. Such dual-stage installation is achieved by utilizing an anchor mounting assembly having a pair or opposite-hand screw-threaded portions thereon which separately mount a blade expanding thrust member and a camming ramp on which the blades are initially expanded by axial movement of the thrust member toward the ramp and in the second stage causing the ramp to axially move toward the thrust member in further expanding relation to the blades.
Abstract translation: 本发明涉及用于固体壁安装的膨胀锚，并且特别涉及提供一种自切割膨胀锚，其可以通过利用组合的切割刀片和壁夹持构件来连续地安装，所述组合切割刀片和壁抓握构件在壁孔内切割自己的底切部分 其中夹持构件然后被永久地进一步扩大为正的锁定接合。 这样的双级安装是通过利用锚固安装组件来实现的，锚具安装组件具有一对或相反的螺纹螺纹部分，其分别安装有叶片膨胀推力构件和凸轮斜面，叶片最初通过推力轴向运动而膨胀 构件朝向斜坡并且在第二阶段中导致斜面朝向推力构件轴向移动，与叶片进一步扩展。
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20.发明授权Polymeric foam tube insulations and method for continuously producing such a tube 失效聚合泡沫管绝缘和连续生产这种管的方法
公开(公告)号：US07854240B2
公开(公告)日：2010-12-21
申请号：US10564822
申请日：2003-07-18
Applicant: Mika Meller , Juerg Weibel , Stephen C. Davis , Scott A. White , Charles Princell
Inventor： Mika Meller , Juerg Weibel , Stephen C. Davis , Scott A. White , Charles Princell
IPC: F16L9/14
CPC classification number: B05D1/16 , B29C44/56 , F16L59/021
Abstract: The foam tube for pipe insulations has an external surface and an internal surface. The internal surface is provided with an adhesively bonded layer of fibers. The fibers are a material having a melt temperature that is higher than that of the polymeric foam. The fibers are adhesively bonded to the internal surface such as to stand up from the internal surface. The fibers are substantially uniformly distributed over the internal surface providing a surface coverage of 2 to 20 percent. Further, the fibers have a linear density of 0.5 to 25 dtex and a length of 0.2 to 5 mm. With this fiber layer the polymeric foam tube has an improved thermal resistance and thermal conductivity.
Abstract translation: 用于管道绝缘的泡沫管具有外表面和内表面。 内表面设置有粘合的纤维层。 纤维是具有高于聚合物泡沫的熔体温度的材料。 纤维粘合到内表面，以便从内表面起立。 纤维基本上均匀地分布在内表面上，提供2至20％的表面覆盖率。 此外，纤维的线密度为0.5〜25dtex，长度为0.2〜5mm。 对于该纤维层，聚合物泡沫管具有改进的耐热性和导热性。
