公开(公告)号：US20110200161A1

公开(公告)日：2011-08-18

申请号：US12836774

申请日：2010-07-15

Applicant: Aleksandar M. Tasic ,  Junxiong Deng ,  Dongjiang Qiao

Inventor： Aleksandar M. Tasic ,  Junxiong Deng ,  Dongjiang Qiao

IPC: H03K21/00

CPC classification number: H03K21/08 ,  H03K23/66 ,  H03L7/1976

Abstract: A divide-by-three circuit includes a chain of three dynamic flip-flops and a feedback circuit of combinatorial logic. The divide-by-three circuit receives a clock signal that synchronously clocks each dynamic flip-flop. The feedback circuit supplies a feedback signal onto the first dynamic-flop of the chain. In a first mode, a signal from a slave stage of the first flip-flop and a signal from a slave stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. In a second mode, a signal from a master stage of the first flip-flop and a signal from a master stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. By proper selection of the mode, the frequency range of the overall divider is extended. Combinatorial logic converts thirty-three percent duty cycle signals from the flip-flop chain into fifty percent duty cycle quadrature signals.

Abstract translation: 三分之一电路包括三个动态触发器链和组合逻辑的反馈电路。 分频电路接收时钟信号，同步地对每个动态触发器进行时钟。 反馈电路将反馈信号提供给链的第一动态触发器。 在第一模式中，来自第一触发器的从动级的信号和来自第二触发器的从动级的信号由反馈电路用于产生反馈信号。 在第二模式中，来自第一触发器的主级的信号和来自第二触发器的主级的信号由反馈电路用于产生反馈信号。 通过正确选择该模式，扩展整体分频器的频率范围。 组合逻辑将三十三％的占空比信号从触发器链转换为五十％的占空比正交信号。

公开(公告)号：US07904045B2

公开(公告)日：2011-03-08

申请号：US11771267

申请日：2007-06-29

Applicant: Ichiro Aoki ,  Scott D. Kee ,  Dongjiang Qiao ,  Alyosha C. Molnar

Inventor： Ichiro Aoki ,  Scott D. Kee ,  Dongjiang Qiao ,  Alyosha C. Molnar

IPC: H04B1/06

CPC classification number: H03L7/0812 ,  H03L7/085 ,  H03L7/087

Abstract: A phase detector includes a plurality of phase detectors located in a phase correction loop, each phase detector configured to receive as input a radio frequency (RF) input signal and an RF reference signal, each of the plurality of phase detectors also configured to provide a signal representing a different phase offset based on the phase difference between the RE input signal and the RF reference signal; and a switch configured to receive an output of each of the plurality of phase detectors and configured to select the output representing the phase offset, that is closest to a phase of an output of an amplifier.

Abstract translation: 相位检测器包括位于相位校正回路中的多个相位检测器，每个相位检测器被配置为接收射频（RF）输入信号和RF参考信号作为输入，多个相位检测器中的每一个还被配置为提供一个 基于RE输入信号和RF参考信号之间的相位差表示不同的相位偏移的信号; 以及开关，被配置为接收所述多个相位检测器中的每一个的输出，并被配置为选择表示最接近放大器的输出的相位的相位偏移的输出。

公开(公告)号：US08570076B2

公开(公告)日：2013-10-29

申请号：US12829107

申请日：2010-07-01

Applicant: Gary L. Brown ,  Alberto Cicalini ,  Dongjiang Qiao

Inventor： Gary L. Brown ,  Alberto Cicalini ,  Dongjiang Qiao

IPC: H03B19/06

CPC classification number: H03L7/00 ,  H03K23/667 ,  H03K23/68

Abstract: A parallel path frequency divider (PPFD) includes a low power frequency divider and a high speed latch. A first portion of an oscillating input signal present on an input node of the PPFD is communicated to the divider and a second portion is communicated to the latch. The divider generates a frequency divided enable signal that is communicated to the latch. The latch generates a divided down output signal based on the oscillating input signal and the enable signal. The output signal is insensitive to phase noise present on the enable signal as long as the phase noise on the enable signal is less than one-half of the period of oscillation of the oscillating input signal. Because the noise generated by the low power frequency divider is not propagated to the output signal generated by the PPFD, the PPFD generates low noise, frequency divided signals with relatively low power consumption.

Abstract translation: 并行路径分频器（PPFD）包括低功耗分频器和高速锁存器。 存在于PPFD的输入节点上的振荡输入信号的第一部分被传送到分频器，并且第二部分被传送到锁存器。 分频器产生与锁存器通信的分频使能信号。 锁存器基于振荡输入信号和使能信号产生分频输出信号。 输出信号对使能信号中存在的相位噪声不敏感，只要使能信号的相位噪声小于振荡输入信号的振荡周期的一半即可。 由于低功耗分频器产生的噪声不会传播到由PPFD产生的输出信号，所以PPFD产生低噪声，分频信号，功耗相对较低。

公开(公告)号：US20120001666A1

公开(公告)日：2012-01-05

申请号：US12829107

申请日：2010-07-01

Applicant: Gary L. Brown ,  Alberto Cicalini ,  Dongjiang Qiao

Inventor： Gary L. Brown ,  Alberto Cicalini ,  Dongjiang Qiao

IPC: H03B19/06

CPC classification number: H03L7/00 ,  H03K23/667 ,  H03K23/68

Abstract: A parallel path frequency divider (PPFD) includes a low power frequency divider and a high speed latch. A first portion of an oscillating input signal present on an input node of the PPFD is communicated to the divider and a second portion is communicated to the latch. The divider generates a frequency divided enable signal that is communicated to the latch. The latch generates a divided down output signal based on the oscillating input signal and the enable signal. The output signal is insensitive to phase noise present on the enable signal as long as the phase noise on the enable signal is less than one-half of the period of oscillation of the oscillating input signal. Because the noise generated by the low power frequency divider is not propagated to the output signal generated by the PPFD, the PPFD generates low noise, frequency divided signals with relatively low power consumption.

Abstract translation: 并行路径分频器（PPFD）包括低功耗分频器和高速锁存器。 存在于PPFD的输入节点上的振荡输入信号的第一部分被传送到分频器，并且第二部分被传送到锁存器。 分频器产生与锁存器通信的分频使能信号。 锁存器基于振荡输入信号和使能信号产生分频输出信号。 输出信号对使能信号中存在的相位噪声不敏感，只要使能信号的相位噪声小于振荡输入信号的振荡周期的一半即可。 由于低功耗分频器产生的噪声不会传播到由PPFD产生的输出信号，所以PPFD产生低噪声，分频信号，功耗相对较低。