公开(公告)号：US06219754B1

公开(公告)日：2001-04-17

申请号：US08994489

申请日：1997-12-19

Applicant: Steven L. Belt ,  Douglas D. Gephardt ,  Drew J. Dutton ,  Brett B. Stewart ,  Rita M. Wisor

Inventor： Steven L. Belt ,  Douglas D. Gephardt ,  Drew J. Dutton ,  Brett B. Stewart ,  Rita M. Wisor

IPC: G06F1200

CPC classification number: G06F12/0875

Abstract: A dedicated bus between a central processing unit and a peripheral unit, such as a graphics controller driving a video display, provides enhanced capability in an environment in which signal processing occurs within the central processing unit. The dedicated bus relieves other data buses, such as the PCI bus, of the need to communicate large amounts of data, such as decompressed video data. The resulting system supports high bandwidth transmissions of decompressed video data, enabling high resolution 24 bit full motion video and multiple data stream video.

Abstract translation: 在中央处理单元和周边单元之间的专用总线，例如驱动视频显示器的图形控制器，在中央处理单元内发生信号处理的环境中提供增强的能力。 专用总线减轻了诸如PCI总线的其他数据总线，需要传送大量数据，例如解压缩的视频数据。 所得到的系统支持解压缩视频数据的高带宽传输，实现高分辨率24位全动态视频和多数据流视频。

公开(公告)号：US5625829A

公开(公告)日：1997-04-29

申请号：US276250

申请日：1994-07-18

Applicant: Douglas D. Gephardt ,  Steven L. Belt ,  Drew J. Dutton

Inventor： Douglas D. Gephardt ,  Steven L. Belt ,  Drew J. Dutton

IPC: G06F15/173 ,  G06F1/16 ,  G06F13/36 ,  G06F13/364 ,  G06F13/40 ,  G06F3/00

CPC classification number: G06F13/364 ,  G06F1/1632 ,  G06F13/4036 ,  G06F13/4081

Abstract: A dockable computer system is capable of performing symmetrical multi-processing operations. More particularly, the dockable computer system includes a portable computer and a host station (docking station), each including a resident CPU. The dockable computer system is capable of operating in a docked state in which the portable computer is physically joined with the host station and an undocked state in which the portable computer is physically separate from the host station. In the docked state, the dockable computer system is capable of performing demanding computational tasks such as video conferencing as one of the CPUs in either the portable computer or host station is dedicated to the video conferencing operation. The dockable computer system preferably includes a communication channel for transmitting multi-processing support signals between the portable computer and the host station. Multi-processing support signals include synchronization signals, cache coherency signals, and interrupt distribution signals such as the LOCK signal, PLOCK signal, FLUSH signal, EADS signal, INTR signal or INTACK signal. The communication channel may be a dedicated bus or may be provided through a docking bridge between the portable computer and host station. The dockable computer system advantageously optimizes CPU resources when the dockable computer system is in a docked state.

Abstract translation: 可停靠的计算机系统能够执行对称的多处理操作。 更具体地，可停靠的计算机系统包括便携式计算机和主机站（对接站），每个都包括驻留的CPU。 可停靠的计算机系统能够在对接状态下操作，其中便携式计算机与主机站物理连接，并且其中便携式计算机在物理上与主机站分离的未停靠状态。 在对接状态下，可停靠的计算机系统能够执行诸如视频会议的苛刻的计算任务，因为便携式计算机或主机站中的一个CPU专用于视频会议操作。 对接计算机系统优选地包括用于在便携式计算机和主机站之间传送多处理支持信号的通信信道。 多处理支持信号包括同步信号，高速缓存一致性信号和中断分配信号，例如LOCK信号，PLOCK信号，FLUSH信号，EADS信号，INTR信号或INTACK信号。 通信信道可以是专用总线，或者可以通过便携式计算机和主机站之间的对接桥提供。 可对接计算机系统有利地优化当可停靠的计算机系统处于对接状态时的CPU资源。

公开(公告)号：US5142672A

公开(公告)日：1992-08-25

申请号：US132296

申请日：1987-12-15

Applicant: William M. Johnson ,  Timothy A. Olson ,  Drew J. Dutton ,  Sherman Lee ,  David W. Stoenner

Inventor： William M. Johnson ,  Timothy A. Olson ,  Drew J. Dutton ,  Sherman Lee ,  David W. Stoenner

IPC: G06F13/28 ,  G06F13/36

CPC classification number: G06F13/28

Abstract: Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the above transfer function in a manner that facilitates communication between the first and second set of devices from the compartively lower performance of the second set of devices. According to the preferred embodiment of the invention, a data transfer controller i.e., ("DTC") is disclosed that includes a set of direct memory access ("DMA") channels and an input/output controller comprising a set of address mapped I/O ports. Both the DMA channels and I/O ports may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting DTC interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance.

公开(公告)号：US08572420B2

公开(公告)日：2013-10-29

申请号：US11071961

申请日：2005-03-04

Applicant: Drew J. Dutton ,  James R. MacDonald ,  Henry Wurzburg

Inventor： Drew J. Dutton ,  James R. MacDonald ,  Henry Wurzburg

IPC: G06F3/00

CPC classification number: G06K19/07732 ,  G06K7/0013 ,  G06K7/0086 ,  G06K19/0701

Abstract: In various embodiments, a computer system may include a computer controller to send and/or receive sideband signals to/from a USB device. In some embodiments, the USB device may include a USB controller to send/receive sideband signals to/from the computer controller. The computer controller and USB controller may allow communications between the computer system and the USB device when either of the computer system or USB device is in a low power state. The sideband signal sent between the computer system and the USB device may trigger the other of the computer system or USB device to enter a normal power state. In some embodiments, the computer controller and/or USB controller may be further coupled to a memory to buffer data to be sent to the computer system or USB device after the computer system or USB device returns to a normal power state.

Abstract translation: 在各种实施例中，计算机系统可以包括计算机控制器来向/从USB设备发送和/或接收边带信号。 在一些实施例中，USB设备可以包括用于向计算机控制器发送/接收边带信号的USB控制器。 当计算机系统或USB设备中的任一个处于低功率状态时，计算机控制器和USB控制器可以允许计算机系统和USB设备之间的通信。 在计算机系统和USB设备之间发送的边带信号可能触发计算机系统或USB设备中的另一个进入正常的电源状态。 在一些实施例中，计算机控制器和/或USB控制器可以进一步耦合到存储器，以在计算机系统或USB设备恢复到正常功率状态之后缓冲要发送到计算机系统或USB设备的数据。

公开(公告)号：US07930576B2

公开(公告)日：2011-04-19

申请号：US11958601

申请日：2007-12-18

Applicant: Ian F. Harris ,  Drew J. Dutton

Inventor： Ian F. Harris ,  Drew J. Dutton

IPC: G06F1/26 ,  G06F15/177

CPC classification number: G06F13/16

Abstract: System and method for sharing a device, e.g., non-volatile memory, between a host processor and a microcontroller. In response to system state change to a first state wherein the microcontroller is assured safe access to the non-volatile memory (e.g., in response to power-on reset, system reset, sleep state, etc.), the microcontroller holds the system in the first state (e.g., system reset), and switches access to the non-volatile memory from the processor to the microcontroller. While the system is held in the first state, the microcontroller accesses the device (e.g., non-volatile memory), e.g., fetches program instructions/data from the non-volatile memory and loads the program instructions/data into a memory of the microcontroller. After the access, the microcontroller changes or allows change of the system state, e.g., switches access to the device, e.g., the non-volatile memory, from the microcontroller to the processor, and releases the system from the first state.

Abstract translation: 用于在主处理器和微控制器之间共享设备（例如，非易失性存储器）的系统和方法。 响应于系统状态改变到第一状态，其中微控制器被安全地访问非易失性存储器（例如，响应于上电复位，系统复位，睡眠状态等），微控制器将系统保持在 第一个状态（例如，系统复位），并切换从处理器到微控制器的非易失性存储器的访问。 当系统处于第一状态时，微控制器访问设备（例如，非易失性存储器），例如从非易失性存储器获取程序指令/数据，并将程序指令/数据加载到微控制器的存储器中 。 在访问之后，微控制器改变或允许系统状态的改变，例如，将从该微控制器的设备（例如，非易失性存储器）的访问切换到处理器，并将系统从第一状态释放。

公开(公告)号：US20090058429A1

公开(公告)日：2009-03-05

申请号：US11870529

申请日：2007-10-11

Applicant: Ian F. Harris ,  Drew J. Dutton ,  Kenneth W. Gay

Inventor： Ian F. Harris ,  Drew J. Dutton ,  Kenneth W. Gay

IPC: G01R27/26

CPC classification number: G06F1/1679 ,  G06F1/1616 ,  H03K17/975 ,  H04M1/0245 ,  H04M2250/12 ,  H04W52/0251 ,  Y02D70/168

Abstract: System and method for determining closure of an electronic device. The electronic device may include a top portion and a bottom portion, and may be connecting via a hinge or other closing mechanism. The top portion and/or the bottom portion may include one or more capacitive sensors which provide signals corresponding to physical contact and a controller coupled to the one or more capacitive sensors. The controller may operate to receive the signals from the one or more capacitive sensors, determine if the electronic device has been closed based on the received signals, and initiate a sequence of events corresponding to the closure of the electronic device. The sequence of events may result in the device entering a low power state.

Abstract translation: 用于确定电子设备闭合的系统和方法。 电子设备可以包括顶部和底部，并且可以经由铰链或其他关闭机构连接​​。 顶部和/或底部可以包括提供对应于物理接触的信号的一个或多个电容式传感器，以及耦合到一个或多个电容式传感器的控制器。 控制器可以操作以接收来自一个或多个电容式传感器的信号，基于接收到的信号确定电子设备是否已经被关闭，并且启动与电子设备的关闭对应的事件序列。 事件的顺序可能导致设备进入低功率状态。

公开(公告)号：US06883105B2

公开(公告)日：2005-04-19

申请号：US10004390

申请日：2001-10-25

Applicant: Drew J. Dutton

Inventor： Drew J. Dutton

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3215

Abstract: A method and apparatus for configuration control and power management through special signaling is provided. In one embodiment, a computer system may include a processor and a plurality of devices that may act as a source device, a destination device, or both. A particular source device may be configured for communications with a destination device. The source device may further be configured to violate one or more known communications rules when communicating the with the destination device. The destination device may be configured to detect the violation. The violation of a known communications rule by the source device may indicate a pending change of state in the computer system, or that a change of state has occurred.

Abstract translation: 提供了一种通过特殊信令进行配置控制和电源管理的方法和装置。 在一个实施例中，计算机系统可以包括可以充当源设备，目的地设备或两者的处理器和多个设备。 可以将特定源设备配置为与目的地设备进行通信。 源设备还可以被配置为在与目的地设备通信时违反一个或多个已知通信规则。 目的地设备可以被配置为检测违规。 由源设备违反已知的通信规则可以指示计算机系统中的待决状态改变，或者已经发生状态改变。

公开(公告)号：US5802330A

公开(公告)日：1998-09-01

申请号：US644405

申请日：1996-05-01

Applicant: Drew J. Dutton

Inventor： Drew J. Dutton

IPC: G06F13/364 ,  G06F13/18

CPC classification number: G06F13/364

Abstract: A computer system includes a bus arbiter for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for generating corresponding grant signals to indicate a grant of ownership of the bus. A set of programmable registers are provided to receive configuration information for controlling the relative priority given to each of the bus masters when bus request contention occurs. One or more of the bus masters includes an arbitration feedback control circuit and feedback register for generating and storing a value to indicate whether the latency in obtaining the bus during a previous bus request phase was generous, was acceptable, or was longer than desired (i.e., the latency requirement for the device was either violated or the latency in obtaining the bus reached a near-critical point). If the value in the feedback register of a particular peripheral indicates the master desires faster access to the bus, an arbitration control unit of the bus arbiter increases a level of arbitration priority given to that master for future bus requests. Similarly, if the value in the feedback register of a peripheral indicates the master received ownership of the bus during a previous bus request phase with ample time, the arbitration control unit may decrease a level of arbitration priority given to the device.

Abstract translation: 计算机系统包括总线仲裁器，用于控制总线的所有权，多个实时和非实时资源都耦合到总线上。 总线仲裁器包括用于检测多个总线主机的总线请求信号的请求检测单元，以及用于产生相应的授权信号的授权发生器，用于指示总线的所有权授权。 提供一组可编程寄存器以接收配置信息，用于当发生总线请求争用时控制给予每个总线主机的相对优先级。 一个或多个总线主机包括仲裁反馈控制电路和反馈寄存器，用于产生和存储一个值，以指示在先前的总线请求阶段期间获得总线的延迟是否是大的，是可接受的，或者比期望的长（即 ，设备的等待时间要求被侵犯或获得总线的延迟达到了临近点）。 如果特定外设的反馈寄存器中的值指示主机希望更快地访问总线，则总线仲裁器的仲裁控制单元增加给予该主机的未来总线请求的仲裁优先级。 类似地，如果外设的反馈寄存器中的值指示主机在具有足够时间的先前总线请求阶段期间接收到总线的所有权，则仲裁控制单元可以降低给予该设备的仲裁优先级。

公开(公告)号：US5680578A

公开(公告)日：1997-10-21

申请号：US479782

申请日：1995-06-07

Applicant: Drew J. Dutton ,  David S. Christie

Inventor： Drew J. Dutton ,  David S. Christie

IPC: G06F9/318 ,  G06F9/38 ,  G06F12/00

CPC classification number: G06F9/30185 ,  G06F9/34 ,  G06F9/3844

Abstract: A microprocessor is provided which expands the functionality and/or performance of the implemented architecture in transparent and/or non-transparent ways. The microprocessor is configured to detect the presence of segment override prefixes in instruction code sequences being executed in flat memory mode and to use the prefix value to control internal and/or external functions. Additionally, the microprocessor may be configured to signal a change or modification of the normal execution of the instruction(s) which follow. Many embodiments are shown which use the segment override prefixes to expand the performance or capability of the microprocessor. Backward compatibility with older implementations of the x86 architecture may be maintained when implementing transparent embodiments.

Abstract translation: 提供了一种微处理器，其以透明和/或不透明的方式扩展了实施的架构的功能和/或性能。 微处理器被配置为检测在平面存储器模式下执行的指令代码序列中是否存在段重写前缀，并且使用前缀值来控制内部和/或外部功能。 另外，微处理器可以被配置为发信号通知随后的指令的正常执行的改变或修改。 示出了使用段重写前缀来扩展微处理器的性能或能力的许多实施例。 在实现透明实施例时，可以维护与旧版本的x86架构的向后兼容性。

公开(公告)号：US20140251517A1

公开(公告)日：2014-09-11

申请号：US14281260

申请日：2014-05-19

Applicant: Drew J. Dutton

Inventor： Drew J. Dutton

IPC: B60B9/04

CPC classification number: B60B9/04 ,  B60B9/26

Abstract: An interlocking, compressible spoke wheel system having a ring of paired spokes. The locking of left and right spokes into pairs provides improved tire displacement under loads. The left and right half wheels formed by sets of left spokes and right spokes. enable a novel mounting system for the wheel rim or tire to attach to the spoke system.

Abstract translation: 具有成对辐条环的互锁的可压缩辐条轮系统。 将左右轮辐锁定成对可以提供改善的载荷下的轮胎位移。 由左侧辐条和右辐条组成的左右半轮。 使得轮缘或轮胎的新型安装系统能够附接到辐条系统。