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公开(公告)号：US08735857B2
公开(公告)日：2014-05-27
申请号：US13271679
申请日：2011-10-12
CPC分类号： H03K19/17728 , H03K19/17796
摘要： A via-configurable circuit block may contain chains of p-type and n-type transistors that may or may not be interconnected by means of configurable vias. Configurable vias may also be used to connect various transistor terminals to a ground line, a power line and/or to various terminals that may provide connections outside of the circuit block.
摘要翻译： 通孔可配置电路块可以包含可以或可以不通过可配置通孔互连的p型和n型晶体管链。 可配置的通孔也可用于将各种晶体管端子连接到接地线，电力线和/或可提供电路块外部的连接的各种端子。
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12.发明授权公开(公告)号：US08566769B2
公开(公告)日：2013-10-22
申请号：US13547884
申请日：2012-07-12
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译： 提供了一种使用存储器定时数据库的方法和装置。 定义了多个表征存储器，其可被映射到存储器资源。 每个表征存储器具有不同的存储器参数。 还定义了将每个表征存储器平铺到存储器资源的多种变型。 每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。
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公开(公告)号：US20110258587A1
公开(公告)日：2011-10-20
申请号：US13173855
申请日：2011-06-30
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.
摘要翻译： 根据各种实施例，提供了一种用于减少信号延迟偏差的系统和方法。 本公开的一个说明性实施例涉及一种方法。 根据一个说明性实施例，该方法包括：接收在组件之间具有组件和连接路径的初始网表; 识别所述初始网表中的第一连接路径，其包括在所述初始网表中的第二连接路径中不存在等效路径片段的路径片段; 生成偏差校正网表，其中所述第二连接路径被重新路由以具有等同于所述第一连接路径的路径片段的路径片段; 并输出偏差校正的网表。
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公开(公告)号：US07856577B2
公开(公告)日：2010-12-21
申请号：US11944104
申请日：2007-11-21
IPC分类号： G06F11/00
摘要： A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing.
摘要翻译： 提供了一种用于测试电子存储器件中的多个存储器位置的存储器测试系统。 该系统包括集成到能够接收和存储编译的存储器测试程序的电子存储器件中的可编程存储器件。 处理器与可编程存储器设备进行通信，以读取和执行存储在可编程存储器设备中的已编译测试程序的指令，并且命令解释器被配置为从存储器测试期间执行的命令接收来自处理器的数据。
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公开(公告)号：US07739471B2
公开(公告)日：2010-06-15
申请号：US11256830
申请日：2005-10-24
IPC分类号： G06F12/02
CPC分类号： G11C8/12 , G11C2207/104
摘要： A method of configuring a random access memory matrix containing partially configured memories in the matrix. The method includes the steps of independently calculating a memory enable signal and a configuration signal for a partially configured memory in each memory tile of the memory matrix. Memory tiles not supported by a memory compiler are determined. A memory wrapper is provided for each tile not supported by the memory compiler. An address controller is inserted in the memory matrix for each tile in a group of tiles. Output signals from each memory location in a memory group having a common group index are combined into a single output signal. A first stripe of memory tiles containing non-configured memory having a first width is selected. A second strip of memory tiles containing configured memory having a second width is also selected.
摘要翻译： 一种在矩阵中配置包含部分配置的存储器的随机存取存储器矩阵的方法。 该方法包括以下步骤：对存储器矩阵的每个存储器块中的部分配置的存储器独立地计算存储器使能信号和配置信号。 确定内存编译器不支持的内存片。 为存储器编译器不支持的每个片提供内存包装器。 在一组瓦片中的每个瓦片的存储矩阵中插入地址控制器。 来自具有公共组索引的存储器组中的每个存储器位置的输出信号被组合成单个输出信号。 选择包含具有第一宽度的非配置存储器的第一条存储器片。 还选择包含具有第二宽度的配置存储器的第二条存储器片。
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16.发明申请公开(公告)号：US20100023904A1
公开(公告)日：2010-01-28
申请号：US12508320
申请日：2009-07-23
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译： 提供了一种用于创建和使用存储器定时数据库的方法和装置。 定义了多个表征存储器，其可被映射到存储器资源。 每个表征存储器具有不同的存储器参数。 还定义了将每个表征存储器平铺到存储器资源的多种变型。 每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。
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17.发明申请Generation Of Test Sequences During Memory Built-In Self Testing Of Multiple Memories 有权在多个记忆的内存自检过程中产生测试序列公开(公告)号：US20090316507A1
公开(公告)日：2009-12-24
申请号：US12142912
申请日：2008-06-20
CPC分类号： G11C29/16 , G11C2029/0401 , G11C2029/2602
摘要： The present invention concerns an apparatus including a modular memory and an address locator circuit. The modular memory may be configured to generate a current address signal, a first data output signal and a second data output signal in response to a first port address signal, a second port address signal, an initial state parameter, a target state parameter, a first port enable signal, a second port enable signal, a write enable signal, a data input signal, a first location signal and a second location signal. The address locator circuit may be configured to generate the first location signal and the second location signal in response to the first port address signal, the second port address signal and the current address signal.
摘要翻译： 本发明涉及一种包括模块化存储器和地址定位器电路的装置。 模块化存储器可以被配置为响应于第一端口地址信号，第二端口地址信号，初始状态参数，目标状态参数，等等，产生当前地址信号，第一数据输出信号和第二数据输出信号 第一端口使能信号，第二端口使能信号，写使能信号，数据输入信号，第一位置信号和第二位置信号。 地址定位器电路可以被配置为响应于第一端口地址信号，第二端口地址信号和当前地址信号而产生第一位置信号和第二位置信号。
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公开(公告)号：US20090281969A1
公开(公告)日：2009-11-12
申请号：US12117851
申请日：2008-05-09
IPC分类号： G06F15/18
CPC分类号： G06F17/505
摘要： An arbitrary function may be represented as an optimized decision tree. The decision tree may be calculated, pruned, and factored to create a highly optimized set of equations, much of which may be represented by simple circuits and little, if any, complex processing. A circuit design system may automate the decision tree generation, optimization, and circuit generation for an arbitrary function. The circuits may be used for processing digital signals, such as soft decoding and other processes, among other uses.
摘要翻译： 任意函数可以表示为优化决策树。 决策树可以被计算，修剪和因子分解以创建高度优化的方程组，其中大部分可以由简单的电路和很少的（如果有的话）复杂的处理来表示。 电路设计系统可以自动执行任意功能的决策树生成，优化和电路生成。 这些电路可以用于处理数字信号，诸如软解码和其他处理以及其它用途。
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公开(公告)号：US20090187873A1
公开(公告)日：2009-07-23
申请号：US12015925
申请日：2008-01-17
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.
摘要翻译： 根据各种实施例，公开了一种用于减小信号延迟偏差的系统。 本公开的一个说明性实施例涉及一种方法。 根据一个说明性实施例，该方法包括接收包括组件之间的组件和连接路径的初始网表。 该方法还包括识别在初始网表中的第一连接路径中的一个或多个偏斜影响特征，其在初始网表中的第二连接路径中缺少对应的偏斜影响特征。 该方法还包括生成偏差校正网表，其中第二连接路径包括与第一连接路径的相应的一个或多个相加的偏斜影响特征。 该方法还包括输出经偏斜校正的网表。
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公开(公告)号：US20080178057A1
公开(公告)日：2008-07-24
申请号：US11626400
申请日：2007-01-24
IPC分类号： H03M13/00
CPC分类号： H03M13/1145
摘要： An improvement to an arithmetic unit of a low-density parity-check decoder, where the arithmetic unit has a pipelined architecture of modules. A first module calculates a difference between absolute values of md_R and md_g_in, and passes the result to a first Gallager module. The first Gallager module converts this value from a p0/p1 representation to a 2*p0−1 representation, and passes the result to a second module. The second module selectively adjusts the result of the previous module based on the sign values of md_g_in and md_R, and passes one of its outputs to a third module (the other two outputs, loc_item_out and hard_out, are not a part of the pipeline). The third module calculates a new md_g value by adding the result of the second module and loc_item_in, and passes this result to a fourth module. The fourth module separates a sign and an absolute value of the new md_g, and passes the result to a second Gallager module. The second Gallager module converts the result from the 2*p0−1 representation to the p0/p1 representation and the final value leaves the unit as md_g_out. In these calculations, md_R=a check node value from the previous iteration, md_g=an edge value (md_g_in—from the previous iteration, md_g_out—for the next iteration), p0=probability that a value is zero, p1=probability that a value is one, loc_item_in/loc_item_out=intermediate values used for the md_g_out calculation, and hard_out=a bit value estimation for the current iteration of the pipelined arithmetic unit.
摘要翻译： 对低密度奇偶校验解码器的算术单元的改进，其中算术单元具有模块的流水线架构。 第一模块计算md_R和md_g_in的绝对值之间的差值，并将结果传递给第一个Gallager模块。 第一个Gallager模块将该值从p0 / p1表示转换为2 * p0-1表示，并将结果传递给第二个模块。 第二个模块根据md_g_in和md_R的符号值有选择地调整前一个模块的结果，并将其一个输出传递给第三个模块（另外两个输出loc_item_out和hard_out不是流水线的一部分）。 第三个模块通过添加第二个模块的结果和loc_item_in来计算一个新的md_g值，并将该结果传递给第四个模块。 第四个模块分离新的md_g的符号和绝对值，并将结果传递给第二个Gallager模块。 第二个Gallager模块将2 * p0-1表示的结果转换为p0 / p1表示，最终值将单位设为md_g_out。 在这些计算中，md_R =来自前一次迭代的校验节点值，md_g =边缘值（md_g_in - 来自上一次迭代，md_g_out-用于下一次迭代），p0 =值为零的概率，p1 = 值为1，loc_item_in / loc_item_out =用于md_g_out计算的中间值，hard_out =流水线运算单元当前迭代的位值估计。
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