公开(公告)号：US20220206865A1

公开(公告)日：2022-06-30

申请号：US17644961

申请日：2021-12-17

Applicant: Equinix, Inc.

Inventor： Kaladhar Voruganti ,  Danjue Li ,  Lanfa Wang ,  Mustafa Arisoyfu ,  Ravi Kiran Pasula ,  Rodney Martin Elder ,  Zoe Liu

IPC: G06F9/50 ,  G06F11/30 ,  G06F11/34 ,  G06N20/00

Abstract: In general, this disclosure describes techniques for configuring and provisioning, with a distributed artificial intelligence (AI) fabric controller, network resources in an AI fabric for use by AI applications. In one example, the AI fabric controller is configured to discover available resources communicatively coupled to a cloud exchange; obtain a set of candidate solutions, each candidate solution of the set of candidate solutions comprising an AI application and a configuration of resources for use by the AI application; filter, based on one or more execution metrics corresponding to each of the candidate solutions, the set of candidate solutions to generate a filtered set of candidate solutions; generate provisioning scripts for the filtered set of candidate solutions; execute the provisioning scripts to provision resources for each candidate solution in the filtered set of candidate solutions; and create an execution environment for each candidate solution in the filtered set of candidate solutions.

公开(公告)号：US11206095B1

公开(公告)日：2021-12-21

申请号：US16728465

申请日：2019-12-27

Applicant: Equinix, Inc.

Inventor： Lanfa Wang ,  Danjue Li

IPC: H04J3/06 ,  H04W56/00

Abstract: Techniques are disclosed for performing time synchronization for a plurality of computing devices that exhibit asymmetric path delay. In one example, processing circuitry receives data indicative of a graph comprising a plurality of nodes and vertices, wherein each node represents a clock and each vertex represents a bidirectional path between two clocks. Each bidirectional path has a first path delay in a first direction that is different from a second path delay in a second direction. The processing circuitry determines one or more closed loops in the graph and a path delay of the closed loop. The processing circuitry applies a minimization function to the path delay of each closed loop to determine values for the first and second path delays of each bidirectional path. The processing circuitry applies, based on the values for the first and second path delays of each bidirectional path, a time correction to a clock.

公开(公告)号：US10893022B1

公开(公告)日：2021-01-12

申请号：US16228540

申请日：2018-12-20

Applicant: Equinix, Inc.

Inventor： Danjue Li ,  Muhammad Durrani ,  Chen Xi ,  Imam Sheikh

IPC: H04L29/06 ,  H04L12/745 ,  H04L29/08

Abstract: In one example, a method includes receiving, by a first network device via a routing protocol peering session with a peer router in a first autonomous system, a plurality of routing protocol routes to destination addresses, each routing protocol route specifying a network address prefix and an identifier of the autonomous system that originated the routing protocol route; receiving network address prefix ownership information from a distributed ledger storing a plurality of associations between respective network address prefixes and respective autonomous system identifiers of autonomous systems confirmed to own the respective network address prefixes; determining, based at least on the prefix ownership information, whether any of the plurality of routing protocol routes specifies an autonomous system identifier different than specified by the associations; and in response to determining that one of the routes specifies an autonomous system identifier different than specified by the plurality of associations, performing an action.