公开(公告)号：US06825115B1

公开(公告)日：2004-11-30

申请号：US10341436

申请日：2003-01-14

申请人： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

发明人： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC分类号： H01L2144

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28518 ,  H01L29/665

摘要： Dopant deactivation, particularly at the Si/silicide interface, is avoided by forming deep source/drain implants after forming silicide layers on the substrate and activating the source/drain regions by laser thermal annealing. Embodiments include forming source/drain extensions, forming metal silicide layers on the substrate surface and gate electrode, forming preamorphized regions under the metal silicide layers in the substrate, ion implanting to form deep source/drain implants overlapping the preamorphized regions and extending deeper into the substrate then the preamorphized regions, and laser thermal annealing to activate the deep source/drain regions.

摘要翻译： 通过在衬底上形成硅化物层并通过激光热退火来激活源极/漏极区域之后形成深源极/漏极注入来避免掺杂失活，特别是Si /硅化物界面。 实施例包括形成源极/漏极延伸部，在衬底表面上形成金属硅化物层和栅电极，在衬底中的金属硅化物层下方形成预变形区域;离子注入，以形成与预变形区域重叠的深源/漏植入物， 衬底然后是前变形区域，激光热退火激活深源/漏区。

公开(公告)号：US06746944B1

公开(公告)日：2004-06-08

申请号：US10341345

申请日：2003-01-14

申请人： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

发明人： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC分类号： H01L213205

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/7833

摘要： Semiconductor devices with reduced NiSi/Si interface contact resistance are fabricated by forming preamorphized regions in a substrate at a depth overlapping the subsequently formed NiSi/Si interface, ion implanting impurities to form deep source/drain implants overlapping the preamorphized regions deeper in the substrate and laser thermal annealing to activate the deep source/drain regions. Nickel silicide layers are then formed in a main surface of the substrate and on the gate electrode. Embodiments include forming deep source/drain regions with an activated impurity concentration of 1×1020 to 1×1021 atoms/cm3 at the NiSi/Si interface.

摘要翻译： 具有降低的NiSi / Si界面接触电阻的半导体器件通过在与随后形成的NiSi / Si界面重叠的深度的衬底中形成预变形区域，离子注入杂质以形成与衬底中较深的预变形区域重叠的深源/漏注入; 激光热退火激活深源/漏区。 然后在衬底的主表面和栅电极上形成硅化镍层。 实施例包括在NiSi / Si界面处形成具有1×10 20至1×10 21原子/ cm 3的活化杂质浓度的深源/漏区。

公开(公告)号：US06555439B1

公开(公告)日：2003-04-29

申请号：US10021551

申请日：2001-12-18

申请人： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

发明人： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC分类号： H01L2100

CPC分类号： H01L21/324 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/28176 ,  H01L21/28211 ,  H01L29/6659

摘要： A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate, forming source/drain extensions in the substrate, and forming first and second sidewall spacers. Dopants are then implanted within the substrate to form amorphitized source/drain regions in the substrate adjacent to the sidewalls spacers. The amorphitized source/drain regions are partially recrystallized, and laser thermal annealing activates the source/drain regions. The source/drain extensions and sidewall spacers are adjacent to the gate electrode. The source/drain extensions can have a depth of about 50 to 300 angstroms, and the source/drain regions can have a depth of about 400 to 1000 angstroms. Also, the recrystallization reduces the amorphitized source/drain regions by a depth of about 20 to 100 angstroms. A semiconductor device is also disclosed.

摘要翻译： 一种制造MOSFET半导体器件的方法包括在衬底上形成栅电极和在栅电极和衬底之间形成栅极氧化物，在衬底中形成源极/漏极延伸部分，以及形成第一和第二侧壁间隔物。 然后将掺杂剂注入到衬底内以在邻近侧壁间隔物的衬底中形成非晶化的源极/漏极区。 非晶化的源极/漏极区域被部分再结晶，并且激光热退火激活源极/漏极区域。 源极/漏极延伸部和侧壁间隔物与栅电极相邻。 源极/漏极延伸部可以具有约50至300埃的深度，并且源极/漏极区域可以具有约400至1000埃的深度。 此外，重结晶将非晶化的源/漏区减少约20至100埃的深度。 还公开了一种半导体器件。

公开(公告)号：US06551888B1

公开(公告)日：2003-04-22

申请号：US10020496

申请日：2001-12-18

申请人： Cyrus E. Tabery ,  Eric N. Paton ,  Bin Yu ,  Qi Xiang ,  Robert B. Ogle

发明人： Cyrus E. Tabery ,  Eric N. Paton ,  Bin Yu ,  Qi Xiang ,  Robert B. Ogle

IPC分类号： H01L21336

CPC分类号： H01L21/268 ,  H01L21/2026 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, introducing dopants into the substrate, forming a tuning layer over at least a portion of the substrate, and activating the dopants using laser thermal annealing. The tuning layer causes an increase or a decrease in the amount of fluence absorbed by the portion of substrate below the tuning layer in comparison to an amount of fluence absorbed by a portion of substrate not covered by the tuning layer. Additional tuning layers can also be formed over the substrate.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成栅电极，将掺杂剂引入衬底中，在衬底的至少一部分上形成调谐层，并使用激光热退火激活掺杂剂。 与由调谐层未被覆盖的基板的一部分吸收的注量相比，调谐层引起由调谐层下方的基板部分吸收的注量的增加或减少。 也可以在衬底上形成附加的调谐层。

公开(公告)号：US06682973B1

公开(公告)日：2004-01-27

申请号：US10147650

申请日：2002-05-16

申请人： Eric N. Paton ,  Qi Xiang ,  Bin Yu

发明人： Eric N. Paton ,  Qi Xiang ,  Bin Yu

IPC分类号： H01L218242

CPC分类号： H01L21/28185 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/2807 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28291 ,  H01L21/31604 ,  H01L21/31662 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A process for fabricating a semiconductor device having a high-K dielectric layer over a silicon substrate, including steps of growing on the silicon substrate an interfacial layer of a silicon-containing dielectric material; and depositing on the interfacial layer a layer comprising at least one high-K dielectric material, in which the interfacial layer is grown by laser excitation of the silicon substrate in the presence of oxygen, nitrous oxide, nitric oxide, ammonia or a mixture of two or more thereof. In one embodiment, the silicon-containing material is silicon dioxide, silicon nitride, silicon oxynitride or a mixture thereof.

摘要翻译： 一种用于制造在硅衬底上具有高K电介质层的半导体器件的方法，包括在硅衬底上生长含硅介电材料的界面层的步骤; 并且在所述界面层上沉积包含至少一种高K电介质材料的层，其中所述界面层通过在氧，一氧化二氮，一氧化氮，氨或两者的混合物的存在下通过硅衬底的激光激发而生长 或更多。 在一个实施方案中，含硅材料是二氧化硅，氮化硅，氮氧化硅或其混合物。

公开(公告)号：US06787864B2

公开(公告)日：2004-09-07

申请号：US10335492

申请日：2002-12-31

申请人： Eric N. Paton ,  Qi Xiang ,  Paul R. Besser ,  Ming-Ren Lin ,  Minh V. Ngo ,  Haihong Wang

发明人： Eric N. Paton ,  Qi Xiang ,  Paul R. Besser ,  Ming-Ren Lin ,  Minh V. Ngo ,  Haihong Wang

IPC分类号： H01L2972

CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L29/1054 ,  H01L29/4908 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66795 ,  H01L2029/7858

摘要： A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.

公开(公告)号：US20090047770A1

公开(公告)日：2009-02-19

申请号：US12205361

申请日：2008-09-05

申请人： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

发明人： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.

摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温过程可以是ALD过程。

公开(公告)号：US06811448B1

公开(公告)日：2004-11-02

申请号：US10619879

申请日：2003-07-15

申请人： Eric N. Paton ,  Paul R. Besser ,  Qi Xiang

发明人： Eric N. Paton ,  Paul R. Besser ,  Qi Xiang

IPC分类号： H01L21302

CPC分类号： H01L21/02054 ,  H01L21/02046 ,  H01L21/02052 ,  H01L21/28518 ,  H01L29/665

摘要： A fabrication system utilizes a protocol for removing native oxide from a top surface of a wafer. An exposure to a plasma, such as a plasma containing hydrogen and argon can remove the native oxide from the top surface without causing excessive germanium contamination. The protocol can use a hydrogen fluoride dip. The hydrogen fluoride dip can be used before the plasma is used. The protocol allows better silicidation in SMOS devices.

摘要翻译： 制造系统利用用于从晶片顶表面去除自然氧化物的协议。 暴露于等离子体，例如含有氢气和氩气的等离子体可从顶表面除去天然氧化物，而不会引起过量的锗污染。 该方案可以使用氟化氢浸渍。 在使用等离子体之前可以使用氟化氢浸渍。 该协议允许在SMOS器件中更好的硅化。

公开(公告)号：US06764912B1

公开(公告)日：2004-07-20

申请号：US09919943

申请日：2001-08-02

申请人： John Clayton Foster ,  Eric N. Paton ,  Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser ,  Paul L. King

发明人： John Clayton Foster ,  Eric N. Paton ,  Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser ,  Paul L. King

IPC分类号： H01L21336

CPC分类号： H01L21/28194 ,  H01L29/51 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656

摘要： The formation of metal silicides in silicon nitride spacers on a gate electrode causes bridging between a gate electrode and the source and drain regions of a semiconductor device. The bridging is prevented by forming a thin layer of silicon oxide on the silicon nitride spacers prior to forming the metal silicide layers on the device.

摘要翻译： 栅电极上的氮化硅间隔物中的金属硅化物的形成导致栅电极与半导体器件的源区和漏区之间的桥接。 通过在器件上形成金属硅化物层之前在氮化硅间隔物上形成氧化硅薄层来防止桥接。

公开(公告)号：US06602781B1

公开(公告)日：2003-08-05

申请号：US09734207

申请日：2000-12-12

申请人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

发明人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

IPC分类号： H01L2144

CPC分类号： H01L21/28202 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833

摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining a metal within a recess overlying a channel and annealing to cause metal and its overlying silicon to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The metal is removed except for the portion of the metal in the recess. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.

摘要翻译： 实现自对准金属硅化物栅极的方法是通过将金属限制在覆盖沟道的凹槽内并退火以使金属及其上覆的硅相互作用以形成自对准的金属硅化物栅极来实现的。 在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。 除了金属在凹部中的部分之外，除去金属。 进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。