公开(公告)号：US06996651B2

公开(公告)日：2006-02-07

申请号：US10207609

申请日：2002-07-29

申请人： Ned D. Garinger ,  Martin L. Dorr ,  Mark W. Naumann ,  Gary A. Walker

发明人： Ned D. Garinger ,  Martin L. Dorr ,  Mark W. Naumann ,  Gary A. Walker

IPC分类号： G06F13/00

CPC分类号： G06F13/36

摘要： A network with memory device address decoding that enables communication among integrated processing elements, including a network, a processing element and a bus gasket. The network transfers packets between multiple ports, where each port conforms to a consistent port interface protocol. The processing element includes a bus and a memory device programmed with the address of each port, so that a transaction on the bus indicating another port is decoded by the memory device. The bus gasket includes a bus interface that generates packets and a port interface that sends and receives the packets according to the consistent port interface protocol and that uses the decoded address as a destination port address. The memory device may be implemented in any desired manner, such as a memory management unit (MMU) or a direct memory access (DMA) device.

摘要翻译： 具有存储器件地址解码的网络，其能够实现集成处理元件之间的通信，包括网络，处理元件和总线衬垫。 网络在多个端口之间传输数据包，其中每个端口都符合一致的端口接口协议。 处理元件包括总线和用每个端口的地址编程的存储器件，使得指示另一端口的总线上的事务被存储器件解码。 总线衬垫包括一个生成数据包的总线接口和一个根据一致的端口接口协议发送和接收数据包并使用解码的地址作为目标端口地址的端口接口。 存储器设备可以以任何期望的方式来实现，诸如存储器管理单元（MMU）或直接存储器存取（DMA）设备。