公开(公告)号：US20060158300A1

公开(公告)日：2006-07-20

申请号：US11334051

申请日：2006-01-18

Applicant: Gheorghe Korony ,  Robert Heistand

Inventor： Gheorghe Korony ,  Robert Heistand

IPC: H01F5/00

CPC classification number: H01F41/041 ,  H01F17/0006 ,  H01F27/34 ,  H01F2017/0046 ,  H01F2021/125

Abstract: Disclosed is methodology and apparatus for producing a planar inductor having a high quality (Q) factor. The inductor is formed by providing a first, relatively wide coil turn, and at least a pair of relatively more narrow second coil turns, displaced in a different plane from that occupied by the first coil turn. The configuration of such coil turns produces a high value of mutual coupling among the coil turns, resulting in an inductor having a high quality (Q) factor.

Abstract translation: 公开了用于生产具有高质量（Q）因子的平面电感器的方法和装置。 电感器通过提供第一相对较宽的线圈匝和至少一对相对较窄的第二线圈匝来形成，第二线圈匝在与第一线圈匝所占据的平面不同的平面内移位。 这种线圈匝的配置在线匝之间产生高的互耦值，导致具有高质量（Q）因子的电感器。

公开(公告)号：US06459561B1

公开(公告)日：2002-10-01

申请号：US09879803

申请日：2001-06-12

Applicant: John Galvagni ,  Andrew Ritter ,  Gheorghe Korony ,  Sonja Brown

Inventor： John Galvagni ,  Andrew Ritter ,  Gheorghe Korony ,  Sonja Brown

IPC: H01G4228

CPC classification number: H01G2/065 ,  H01G4/232 ,  H01L23/642 ,  H01L2924/0002 ,  H05K1/0231 ,  H01L2924/00

Abstract: An improved low inductance termination scheme is disclosed for grid array capacitors. The enhanced termination scheme provides for shorter termination length and leaves the sides of a capacitive element free from any structure. The area typically taken up by solder lands is reduced, facilitating much closer chip spacing on a circuit board. The arrangement generally includes interleaved dielectric and electrode layers in an interdigitated configuration. Vias are drilled through tabs extending from selected of the electrode layers, and then filled with suitable conductive material. Solder balls may be applied directly to this conductive material, providing a ball grid array (BGA) packaged chip ready to mount on an IC and reflow. Composition of such solder balls is easily varied to comply with specific firing conditions. Such capacitor chips are also compatible with land grid array (LGA) packaging techniques. The subject interdigitated electrode design may be utilized to form a single multilayer capacitor or multiple discrete capacitors. Such a capacitor array may be formed by retaining the external configuration and internally subdividing the electrodes. The resulting low cost, low inductance capacitor is ideal for many high frequency applications requiring decoupling capacitors.

Abstract translation: 公开了一种用于栅格阵列电容器的改进的低电感端接方案。 增强的端接方案提供较短的端接长度并使得电容元件的侧面没有任何结构。 通常由焊盘占据的面积减小，有助于电路板上的芯片间距更小。 该布置通常包括交叉配置的交错电介质层和电极层。 通过从选定的电极层延伸的突片钻出通孔，然后用合适的导电材料填充。 可以将焊球直接施加到该导电材料上，提供准备安装在IC上并回流的球栅阵列（BGA）封装芯片。 这种焊球的组成容易变化以符合特定的烧制条件。 这种电容器芯片也与陆地网格阵列（LGA）封装技术兼容。 主题交叉电极设计可用于形成单个层叠电容器或多个分立电容器。 这样的电容器阵列可以通过保持外部构造并且在内部细分电极而形成。 所产生的低成本低电感电容对于需要去耦电容器的许多高频应用是理想的。