公开(公告)号：US20120326269A1

公开(公告)日：2012-12-27

申请号：US13165087

申请日：2011-06-21

申请人： GRISELDA BONILLA ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon

发明人： GRISELDA BONILLA ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5256 ,  H01L21/768 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.

摘要翻译： 提供线后端的电熔丝结构（BEOL）互连和制造方法。 该方法包括在衬底中与第一底层金属线对齐形成互连通孔，并在衬底中形成电熔丝通孔，露出第二下面的金属线。 该方法还包括用第二底层金属线形成缺陷并用金属填充互连通孔并与第一底层金属线接触，从而形成互连结构。 该方法还包括用金属填充e熔丝通孔并与缺陷和第二下面的金属线接触，从而形成电熔丝结构。

公开(公告)号：US08232646B2

公开(公告)日：2012-07-31

申请号：US12691213

申请日：2010-01-21

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

IPC分类号： H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76846 ,  H01L21/76847 ,  H01L23/522 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line.

摘要翻译： 用于集成电路（IC）器件的互连结构包括形成在电介质层内的金属线，所述金属线在其中具有一个或多个垂直扩散阻挡层; 其中所述一个或多个垂直扩散屏障对应于在所述金属线上方形成的通孔的衬垫材料，所述通孔完全延伸穿过所述金属线的厚度，使得所述通孔的最底部包括所述金属线的一部分 。

公开(公告)号：US08836124B2

公开(公告)日：2014-09-16

申请号：US13414742

申请日：2012-03-08

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Samuel Sung Shik Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali Eliahu Lustig ,  Andrew H. Simon

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Samuel Sung Shik Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali Eliahu Lustig ,  Andrew H. Simon

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5256 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse structure includes within an aperture within a dielectric layer located over a substrate that exposes a conductor contact layer within the substrate a seed layer interposed between the conductor contact layer and another conductor layer. The seed layer includes a doped copper material that includes a dopant immobilized predominantly within the seed layer. The fuse structure may be severed while not severing a conductor interconnect structure also located over the substrate that exposes a second conductor contact layer within a second aperture. In contrast with the fuse structure that includes the doped seed layer having the immobilized dopant, the interconnect structure includes a doped seed layer having a mobile dopant.

摘要翻译： 熔丝结构包括在位于衬底之上的电介质层内的孔内，孔暴露在衬底内的导体接触层，介于导体接触层和另一导体层之间的晶种层。 种子层包括掺杂的铜材料，其包括主要在种子层内固定的掺杂剂。 可以切断熔丝结构，同时不切断也位于衬底上的导体互连结构，所述导体互连结构在第二孔内暴露第二导体接触层。 与包括具有固定化掺杂剂的掺杂种子层的熔丝结构相反，互连结构包括具有可移动掺杂剂的掺杂种子层。

公开(公告)号：US20120249159A1

公开(公告)日：2012-10-04

申请号：US13074407

申请日：2011-03-29

申请人： Ronald G. Filippi ,  Griselda Bonilla ,  Kaushik Chanda ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

发明人： Ronald G. Filippi ,  Griselda Bonilla ,  Kaushik Chanda ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

IPC分类号： G01R31/04 ,  G01R31/02 ,  H01L23/62

CPC分类号： H01L23/5226 ,  G01R31/025 ,  G01R31/04 ,  G01R31/07 ,  G01R31/327 ,  H01L23/5256 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

摘要： A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

摘要翻译： 线路的后端（BEOL）保险丝结构具有一叠通孔。 通孔的堆叠导致高的纵横比，使得通孔内的衬里和种子覆盖较差。 衬里和种子层的弱点导致电迁移（EM）故障的较高概率。 保险丝结构由于衬垫和种子覆盖不良而解决故障。 设计特征允许确定故障发生的位置，确定熔丝编程之后受损区域的程度，并防止损坏的介质区域的进一步传播。

公开(公告)号：US20110175226A1

公开(公告)日：2011-07-21

申请号：US12691213

申请日：2010-01-21

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76846 ,  H01L21/76847 ,  H01L23/522 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line

摘要翻译： 用于集成电路（IC）器件的互连结构包括形成在电介质层内的金属线，所述金属线在其中具有一个或多个垂直扩散阻挡层; 其中所述一个或多个垂直扩散屏障对应于在所述金属线上方形成的通孔的衬垫材料，所述通孔完全延伸穿过所述金属线的厚度，使得所述通孔的最底部包括所述金属线的一部分

公开(公告)号：US09093164B2

公开(公告)日：2015-07-28

申请号：US13298661

申请日：2011-11-17

申请人： Ronald G. Filippi ,  Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon

发明人： Ronald G. Filippi ,  Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon

IPC分类号： H01H85/04 ,  G11C17/16 ,  H01L23/525 ,  H01L23/522 ,  G11C29/00 ,  H01H85/46 ,  H01L23/532

CPC分类号： G11C17/16 ,  G11C29/702 ,  H01H2085/466 ,  H01L23/5226 ,  H01L23/5256 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal fuse structure using redundant vias formed on one metal level in a stacked via metal fuse structure to force failures to occur in the metal level that does not have the redundant vias. The metal fuse structure includes a first dielectric layer having a conductor, a second dielectric layer above the first dielectric layer having a first conductive line and a first via, the first via is on the conductor, the first conductive line is on the first via, the first via is the only electrical connection between the first conductive line and the conductor, and a third dielectric layer above the second dielectric layer having a second conductive line, a second via and a third via, the second via and the third via are both on the first conductive line, the second conductive line is on both the first via and the second via.

摘要翻译： 一种金属熔断器结构，其使用在堆叠的通孔金属熔丝结构中的一个金属层上形成的冗余通孔，以迫使在不具有冗余通孔的金属层中发生故障。 金属熔丝结构包括具有导体的第一电介质层，在第一电介质层之上的第二电介质层，具有第一导电线和第一通孔，第一通孔位于导体上，第一导电线在第一通孔上， 所述第一通孔是所述第一导线与所述导体之间的唯一电连接，并且所述第二电介质层上方的第三电介质层具有第二导电线，第二通孔和第三通孔，所述第二通孔和所述第三通孔均为 在第一导线上，第二导线在第一通孔和第二通孔上。

公开(公告)号：US08633707B2

公开(公告)日：2014-01-21

申请号：US13074407

申请日：2011-03-29

申请人： Ronald G. Filippi ,  Griselda Bonilla ,  Kaushik Chanda ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

发明人： Ronald G. Filippi ,  Griselda Bonilla ,  Kaushik Chanda ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

IPC分类号： G01R31/07

CPC分类号： H01L23/5226 ,  G01R31/025 ,  G01R31/04 ,  G01R31/07 ,  G01R31/327 ,  H01L23/5256 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

摘要： A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

公开(公告)号：US20130214894A1

公开(公告)日：2013-08-22

申请号：US13399266

申请日：2012-02-17

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon

IPC分类号： H01H85/04 ,  H01H69/02

CPC分类号： H01L23/5256 ,  H01H69/02 ,  H01H85/046 ,  H01H2085/0275 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  Y10T29/49107 ,  H01L2924/00

摘要： Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.

公开(公告)号：US20130127584A1

公开(公告)日：2013-05-23

申请号：US13298661

申请日：2011-11-17

申请人： Ronald G. Filippi ,  Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon

发明人： Ronald G. Filippi ,  Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon

IPC分类号： H01H85/04

CPC分类号： G11C17/16 ,  G11C29/702 ,  H01H2085/466 ,  H01L23/5226 ,  H01L23/5256 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal fuse structure using redundant vias. The redundant vias are formed on one metal level in a stacked via metal fuse structure to force failures to occur in the metal level that does not have the redundant vias. The metal fuse structure includes: a first dielectric layer having a metal feature; a second dielectric layer having a first metal connector embedded therein; and a third dielectric layer having a second metal connector embedded therein. The metal connectors include at least one via and one line, and at least one metal connector has at least two vias.

摘要翻译： 使用冗余通孔的金属保险丝结构。 冗余通孔在堆叠的通孔金属熔断器结构中的一个金属层上形成，以迫使在不具有冗余通孔的金属层中发生故障。 金属熔丝结构包括：具有金属特征的第一介电层; 第二电介质层，其中嵌有第一金属连接器; 以及具有嵌入其中的第二金属连接器的第三电介质层。 金属连接器包括至少一个通孔和一条线，并且至少一个金属连接器具有至少两个通孔。

公开(公告)号：US07671362B2

公开(公告)日：2010-03-02

申请号：US11953568

申请日：2007-12-10

申请人： Tibor Bolom ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Paul S. McLaughlin ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert ,  James Werking

发明人： Tibor Bolom ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Paul S. McLaughlin ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert ,  James Werking

IPC分类号： H01L23/58

CPC分类号： H01L22/12 ,  H01L22/34

摘要： A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.

摘要翻译： 集成电路（IC）器件制造的测试结构包括形成在IC晶片的各个区域的多个测试结构链，所述多个测试结构链中的每一个包括一个或多个通孔; 所述一个或多个通孔中的每一个与设置在其上的导电线接触，所述导电线被配置为使得其至少一个尺寸从链到链变化，从而在种子层和衬层层厚度之间产生从链到链的变化， 相同的沉积工艺条件。