公开(公告)号：US11314637B2

公开(公告)日：2022-04-26

申请号：US16888123

申请日：2020-05-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Frank R. Dropps ,  Thomas McGee ,  Michael Malewicki

IPC: G06F12/02 ,  G06F12/084 ,  G06F9/38 ,  G06F9/54 ,  G06F12/123

Abstract: To reduce latency and bandwidth consumption in systems, systems and methods are provided for grouping multiple cache line request messages in a related and speculative manner. That is, multiple cache lines are likely to have the same state and ownership characteristics, and therefore, requests for multiple cache lines can be grouped. Information received in response can be directed to the requesting processor socket, and those speculatively received (not actually requested, but likely to be requested) can be maintained in queue or other memory until a request is received for that information, or until discarded to free up tracking space for new requests.

公开(公告)号：US10970213B2

公开(公告)日：2021-04-06

申请号：US16399455

申请日：2019-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Thomas McGee ,  Michael S. Woodacre ,  Michael Malewicki

IPC: G06F12/0815

Abstract: An apparatus, system, and method of enforcing cache coherency in a multiprocessor shared memory system are disclosed. A request is received from a node controller, to process a cache coherent operation on a memory block in a shared memory. Based on the information included in the request, a determination is made as to whether the request was transmitted from a processor that is remote relative to the memory that includes the memory block referenced in the request. If the request is from a remote processor, a hardware-based cache coherency of the system is disabled, and request is processed according to software-based cache coherency protocols and mechanisms. A coherent read request may be translated to a non-coherent request, such as an immediate read request, which does not trigger tracking or storing state and ownership information of the requested memory block, or trigger communications with processors other than those involved with request. Processing a coherent write request may include transmitting an exclusive read request, which is a request for ownership of the memory block identified in the coherent write request, and transmitting a write acknowledgment to the node controller.