公开(公告)号：US20160275014A1

公开(公告)日：2016-09-22

申请号：US15032329

申请日：2013-10-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Kevin T. Lim ,  Sheng Li ,  Parthasarathy Ranganathan ,  William C. Hallowell

IPC: G06F12/08 ,  G06F3/06

Abstract: According to an example, a processor generates a memory access request and sends the memory access request to a memory module. The processor receives data from the memory module in response to the memory access request when a memory device in the memory module for the memory access request is busy and unable to execute the memory access request.

Abstract translation: 根据示例，处理器生成存储器访问请求并将存储器访问请求发送到存储器模块。 当用于存储器访问请求的存储器模块中的存储器设备忙并且不能执行存储器访问请求时，处理器响应于存储器访问请求从存储器模块接收数据。