公开(公告)号：US08722474B2

公开(公告)日：2014-05-13

申请号：US13592589

申请日：2012-08-23

申请人： Hyung Sup Yoon ,  Byoung-Gue Min ,  Jong Min Lee ,  Seong-Il Kim ,  Dong Min Kang ,  Ho Kyun Ahn ,  Jong-Won Lim ,  Jae Kyoung Mun ,  Eun Soo Nam

发明人： Hyung Sup Yoon ,  Byoung-Gue Min ,  Jong Min Lee ,  Seong-Il Kim ,  Dong Min Kang ,  Ho Kyun Ahn ,  Jong-Won Lim ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H01L21/338

CPC分类号： H01L29/0649 ,  H01L21/28593 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

摘要： Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.

摘要翻译： 本发明公开了一种半导体器件，包括阶梯栅电极和制造该半导体器件的方法。 根据本公开的示例性实施例的半导体器件包括：半导体衬底，其具有包括多个外延层的结构，并且包括形成在其最上部的肖特基层的一部分中的下切割区域; 顺序地形成在半导体衬底上的盖层，第一氮化物层和第二氮化物层，以形成台阶栅极绝缘层图案; 以及通过栅极绝缘层图案沉积耐热金属而形成的阶梯形栅电极，其中下切区域包括形成在栅电极和肖特基层之间的空腔。

公开(公告)号：US20130146944A1

公开(公告)日：2013-06-13

申请号：US13592589

申请日：2012-08-23

申请人： Hyung Sup YOON ,  Byoung-Gue Min ,  Jong Min Lee ,  Seong-II Kim ,  Dong Min Kang ,  Ho Kyun Ahn ,  Jong-Won Lim ,  Jae Kyoung Mun ,  Eun Soo Nam

发明人： Hyung Sup YOON ,  Byoung-Gue Min ,  Jong Min Lee ,  Seong-II Kim ,  Dong Min Kang ,  Ho Kyun Ahn ,  Jong-Won Lim ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H01L29/812 ,  H01L21/338

CPC分类号： H01L29/0649 ,  H01L21/28593 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

摘要： Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.

摘要翻译： 本发明公开了一种半导体器件，包括阶梯栅电极和制造该半导体器件的方法。 根据本公开的示例性实施例的半导体器件包括：半导体衬底，其具有包括多个外延层的结构，并且包括形成在其最上部的肖特基层的一部分中的下切割区域; 顺序地形成在半导体衬底上的盖层，第一氮化物层和第二氮化物层，以形成台阶栅极绝缘层图案; 以及通过栅极绝缘层图案沉积耐热金属而形成的阶梯形栅电极，其中下切区域包括形成在栅电极和肖特基层之间的空腔。

公开(公告)号：US08124489B2

公开(公告)日：2012-02-28

申请号：US12832432

申请日：2010-07-08

申请人： Byoung-Gue Min ,  Jongmin Lee ,  Seong-Il Kim ,  Hyung Sup Yoon

发明人： Byoung-Gue Min ,  Jongmin Lee ,  Seong-Il Kim ,  Hyung Sup Yoon

IPC分类号： H01L21/331

CPC分类号： H01L29/66318 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/66204 ,  H01L29/7371 ,  H01L29/868

摘要： Provided are a monolithic microwave integrated circuit device and a method for forming the same. The method includes: forming an sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer on a Heterojunction Bipolar Transistor (HBT) region and a PIN diode region of a substrate; forming an emitter pattern and an emitter cap pattern in the HBT region and exposing the base layer by patterning the emitter layer and the emitter cap layer; and forming an intrinsic region by doping a portion of the collector layer of the PIN diode region with a first type impurity, the PIN diode region being spaced apart from the HBT region.

摘要翻译： 提供了一种单片微波集成电路器件及其形成方法。 该方法包括：在基底的异质结双极晶体管（HBT）区域和PIN二极管区域上形成子集电极层，集电极层，基极层，发射极层和发射极盖层; 在HBT区域中形成发射极图案和发射极盖图案，并通过图案化发射极层和发射极盖层而使基底层曝光; 并且通过用第一类型杂质掺杂PIN二极管区域的集电极层的一部分来形成本征区域，PIN二极管区域与HBT区域间隔开。

公开(公告)号：US08692371B2

公开(公告)日：2014-04-08

申请号：US13549795

申请日：2012-07-16

申请人： Byoung-Gue Min

发明人： Byoung-Gue Min

IPC分类号： H01L23/48

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L21/743 ,  H01L23/4821 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/8385 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/00

摘要： Disclosed are a semiconductor apparatus and a manufacturing method thereof. The manufacturing method of the semiconductor apparatus includes: forming a semiconductor chip on a semiconductor substrate; adhering a carrier wafer with a plurality of through holes onto the semiconductor chip; polishing the semiconductor substrate; forming a first via hole at the rear side of the polished semiconductor substrate; forming a first metal layer below the polished semiconductor substrate and at the first via hole; and removing the carrier wafer from the polished semiconductor substrate.

摘要翻译： 公开了半导体装置及其制造方法。 半导体装置的制造方法包括：在半导体基板上形成半导体芯片; 将具有多个通孔的载体晶片粘附到所述半导体芯片上; 抛光半导体衬底; 在抛光的半导体衬底的后侧形成第一通孔; 在所述抛光的半导体衬底下方和所述第一通孔处形成第一金属层; 以及从抛光的半导体衬底去除载体晶片。

公开(公告)号：US07364977B2

公开(公告)日：2008-04-29

申请号：US10857655

申请日：2004-05-28

申请人： Byoung-Gue Min ,  Kyung-Ho Lee ,  Seong-Il Kim ,  Jong-Min Lee ,  Chul-Won Ju

发明人： Byoung-Gue Min ,  Kyung-Ho Lee ,  Seong-Il Kim ,  Jong-Min Lee ,  Chul-Won Ju

IPC分类号： H01L21/8222

CPC分类号： H01L29/66318 ,  H01L29/7371

摘要： Disclosed are a heterojunction bipolar transistor and a method of fabricating the same. A first dielectric layer easily etched is deposited on the overall surface of a substrate before an isolation region is defined. The first dielectric layer and a sub-collector layer are selectively etched, and then a second dielectric layer etched at a low etch rate is deposited on the overall surface of the substrate. Via holes are formed in the first and second dielectric layers, and then the first dielectric layer is removed using a difference between etch characteristics of the first and second dielectric layers. Accordingly, a reduction in power gain, generated at the interface of a compound semiconductor and a dielectric insulating layer (the second dielectric layer), can be eliminated.

摘要翻译： 公开了异质结双极晶体管及其制造方法。 在限定隔离区之前，易于蚀刻的第一电介质层沉积在基板的整个表面上。 选择性地蚀刻第一介电层和次集电极层，然后以低蚀刻速率蚀刻的第二电介质层沉积在基板的整个表面上。 在第一和第二电介质层中形成通孔，然后使用第一和第二电介质层的蚀刻特性之间的差异去除第一介电层。 因此，可以消除在化合物半导体和介电绝缘层（第二介电层）的界面处产生的功率增益的降低。

公开(公告)号：US20050133820A1

公开(公告)日：2005-06-23

申请号：US10857655

申请日：2004-05-28

申请人： Byoung-Gue Min ,  Kyung-Ho Lee ,  Seong-Il Kim ,  Jong-Min Lee ,  Chul-Won Ju

发明人： Byoung-Gue Min ,  Kyung-Ho Lee ,  Seong-Il Kim ,  Jong-Min Lee ,  Chul-Won Ju

IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L29/739 ,  H01L21/8222 ,  H01L31/0328

CPC分类号： H01L29/66318 ,  H01L29/7371

摘要： Disclosed are a heterojunction bipolar transistor and a method of fabricating the same. A first dielectric layer easily etched is deposited on the overall surface of a substrate before an isolation region is defined. The first dielectric layer and a sub-collector layer are selectively etched, and then a second dielectric layer etched at a low etch rate is deposited on the overall surface of the substrate. Via holes are formed in the first and second dielectric layers, and then the first dielectric layer is removed using a difference between etch characteristics of the first and second dielectric layers. Accordingly, a reduction in power gain, generated at the interface of a compound semiconductor and a dielectric insulating layer (the second dielectric layer), can be eliminated.

摘要翻译： 公开了异质结双极晶体管及其制造方法。 在限定隔离区之前，易于蚀刻的第一电介质层沉积在基板的整个表面上。 选择性地蚀刻第一介电层和次集电极层，然后以低蚀刻速率蚀刻的第二电介质层沉积在基板的整个表面上。 在第一和第二电介质层中形成通孔，然后使用第一和第二电介质层的蚀刻特性之间的差异去除第一介电层。 因此，可以消除在化合物半导体和介电绝缘层（第二介电层）的界面处产生的功率增益的降低。